This paper analyzes the throughput and the optimal announcement traffic indication message (ATIM) window of the IEEE 802.11 Distributed Coordination Function (DCF) in the power saving mode. An analytical model based on Markov chain model is proposed to express the throughput and the optimal ATIM window in a mathematical form; it is validated by the simulation. The optimal ATIM window size is obtained to maximize the throughput and minimize the power consumption while solving the fairness problem.

A new inductance extraction technique of spiral inductor from measurement fixture is presented. We propose a scalable expression of parasitic inductance for interconnects, and design consideration of test structure accommodating spiral inductor. The simple expression includes mutual inductance between the interconnects with high accuracy. The formula matches a commercial field solver inductance values within 1.4%. The layout of the test structure to reduce magnetic coupling between the spiral and the interconnects allows us to extract the intrinsic inductance of spiral more accurately. The proposed technique requires neither special fixture used for measurement-based method nor skilled worker for precise extraction with the analytical technique used.

This paper introduces a methodology for simulating single-electron-transistor (SET)-based multiple-valued logics (MVLs). First, a physics-based analytical model for SET is described, and then a procedure for extracting parameters from measured characteristics is explained. After that, simulated and experimental results for basic MVL circuits are compared. As an advanced example of SET-based logics, a latched parallel counter, which is one of the most important components in arithmetic circuits, is newly designed and analyzed by a simulation. It is found that a SET-based 7-3 counter can be constructed with less than 1/10 the number of devices needed for a conventional circuit and can operate at a moderate speed with 1/100 the conventional power consumption.

The main issue in real time voice applications over Internet is to investigate a lossless playout without jitter while maintaining playout delay as small as possible. Existing playout algorithms estimate network delay by using timestamps and determine the playout schedule only at the beginning of each talkspurt. Also their scheduled playout time is determined based on a fixed upper playout delay bound over a talkspurt. The sliding adaptive playout algorithm we propose can estimate jitter without using timestamps and its playout time is allowed to slide to a certain extent. The aim of sliding playout schedule is to determine the scheduled playout time at the beginning of each talkspurt based on the playout delay expected under the normal condition where the degree of actual jitter is below the magnitude which is not quite large in relation to variations in the "baseline" delays. Then the proposed algorithm can be effectively applied to minimize the scheduled playout delay while improving the voice quality against a spike which may occur at the beginning of a talkspurt as well as a spike which occurs in the middle of a talkspurt. We develop an analytical model of the general adaptive playout algorithms and analyze the playout buffer performance for different degrees of jitter, different values of the scheduled playout delay, different maximum lengths of delay spikes, and arbitrary tolerable ranges of sliding. Based on the analytical results, we suggest the specific values of parameters used in the sliding algorithm.

Cache memories are small fast memories used to temporarily hold the contents of main memory that are likely to be referenced by processors so as to reduce instruction and data access time. In study of cache performance, most of previous works have employed simulation-based methods. However, that kind of researches cannot precisely explain the obtained results. Moreover, when a new processor is designed, huge simulations must be performed again with several different parameters. This research classifies cache structures for superscalar processors into four types, and then represents analytical model of instruction fetch process for each cache type considering various kinds of architectural parameters such as the frequency of branch instructions in program, cache miss rate, cache miss penalty, branch misprediction frequency, and branch misprediction penalty, and etc. To prove the correctness of the proposed models, we performed extensive simulations and compared the results with the analytical models. Simulation results showed that the proposed model can estimate the expected instruction fetch rate accurately within 10% error in most cases. This paper shows that the increase of cache misses reduces the instruction fetch rate more severely than that of branch misprediction does. The model is also able to provide exact relationship between cache miss and branch misprediction for the instruction fetch analysis. The proposed model can explain the causes of performance degradation that cannot be uncovered by the simulation method only.

The high accuracy which is necessary for modern process simulation often requires the use of Monte-Carlo ion implantation simulation methods with the disadvantage of very long simulation times especially for three-dimensional applications. In this work a new method for an accurate and CPU time efficient three-dimensional simulation of ion implantation is suggested. The approach is based on a combination of the algorithmic capabilities of a fast analytical and the Monte-Carlo simulation method.

RSPICE, a fast timing simulator for large digital MOS circuits, is presented in this paper. A new table-based region-wise linear MOS transistor model and the analytical solution of the generic sub-circuit primitive are applied to calculate the transient response of digital MOS circuits. The body effect of pass transistors is included in the MOS model and the floating capacitor network can be handled by this sub-circuit primitive as well. In RSPICE, MOS transistors with a DC path are grouped into a DC-connected block (DCCB), and DCCBs with a feedback path are combined as a strongly connected component (SCC). RSPICE orders SCCs by Tarjan's algorithm and simulates ordered SCCs one by one. DCCBs are basic cells in RSPICE and any DCCB can be mapped into one or more sub-circuit primitives. In order to calculate the transient response of these primitives analytically, RSPICE approximates the input signals of the primitive by piecewise linear functions. To compromise the simulation accuracy and run time, partial waveform and partial time convergent (PWPTC) combined with dynamic windowing technique is applied to simulate SCCs. Other key issues of RSPICE, such as circuit partition, pass-transistor and floating-capacitor processing, simulation-flow control and waveform modification are also discussed in detail. Compared with HSPICE , the simulation result of RSPICE is very accurate with an error less than 3%, but the speed is 1-2 orders over HSPICE.

Fluctuations of three device parameters (Tox, Nsub, ΔL) based on process fluctuations are taken as cause of device/circuit performances. In-line measured device parameters are approximated by Gaussian functions, and their 2σ values are assigned as boundaries of the performance fluctuations. Measured distributions both for device and curcuit performances are successfully reproduced.

In this paper we present a complete methodology for efficient electro-mechanical characterization of a CMOS compatible MEMS technology. Using an original test structure, the so-called "U-shape cantilever beam," we are able to determine all mechanical characteristics of force sensors constituted with elementary beams in a given technology. A complete set of electro-mechanical relations for the design of Microsystems have also been developed.

Evaluating analytically computer architecture performance is mostly cheap and quick. However, existing analytical performance evaluation techniques usually have a difficult and time-consuming modeling process. Moreover, existing techniques do not support well the capability for finding the bottleneck and its cause of a target system being evaluated. To address the above problems and to enhance analytical performance evaluation technology, in this paper we propose a software tool that accepts system models described in a specification language, generating an executable program that performs the actual performance evaluation. The whole approach is built on a subsystem-oriented performance evaluation tool, which is, in turn, based on a formal subsystem-oriented performance evaluation technique and a subsystem specification language.

In order to develop high-speed ICs, it is important to clarify the relationship between circuit speed and device parameters. An analytical expression for circuit performance is effective for this purpose. This paper describes an analytical toggle frequency expression for Source-Coupled FET Logic (SCFL) frequency dividers. The proposed equation is expressed as the sum of the product of sensitivity coefficients of FET parameters and time constants which are extracted through a small signal transfer function analysis. These sensitivity coefficients are extracted using SPICE simulations. The equation is a simple formula with only five coefficients, which is much smaller than conventional sensitivity analyses. Furthermore, the accuracy of the proposed equation is improved compared to an analytical method based on the small signal transfer function which we previously proposed. The equation can be easily extended to consider interconnection delay time. The calculated maximum toggle frequencies using the equation show good agreement with SPICE simulations and experimental results for a wide gate-length variation range of 0. 12-µm to 0. 24-µm GaAs MESFETs. By re-extraction of another set of sensitivity coefficients, the proposed equation can be widely applied to shorter gate-length GaAs MESFETs and other FET devices such as HEMT devices. The expression clearly shows the relationship between the circuit performance and intrinsic FET parameters. According to the equation, the key parameters for high-speed circuit operation are high transconductance with a low drain conductance, and a low gate-drain capacitance. The equation can be used as a criterion for the optimization of the FET structure to realize high speed circuit performance.

In this paper, we formulate and solve a discrete-time queueing problem that has two potential applications: ATM multiplexers and DQDB networks. We first consider the modeling of an ATM multiplexer. The object of the analysis is a periodic traffic stream (CBR traffic), which is one of the inputs to the multiplexer. As in previous works of the subject, we consider a memoryless background traffic input. Here, in addition to this background traffic, we take into account the influence of a high-priority traffic, which is time-correlated and requires expedited service. We analyze the influence of these two types of traffic on the statistics of the interdeparture time (jitter process) and the delay of the periodic traffic stream. We obtain their distributions in a form of z-transforms, and from these we derive closed form expressions for the average delay and the variance of the interdeparture time. Our results show that the delay and jitter are very sensitive to the burstiness of the high priority traffic arrival process. We next apply our analytical modeling to a DQDB network when some of its stations are driven by CBR sources. We can obtain interesting results concerning the influence of the physical location of a DQDB station on the jitter.

Exact analytical solutions for the steady-state transmission and reflection characteristics of a nonlinear Fabry-Perot resonator applicable to bistable optical devices are derived. The resonator consists of a Kerr-like nonlinear film sandwiched by reflection mirrors made of a quarter-wave dielectric stack. An equivalent mirrorless model has been introduced to facilitate the analysis. For both positive and negative nonlinear coefficients, the rigorous solutions have been simply expressed in terms of Jacobian elliptic functions.

This work describes a new analytical MOSFET model for analog circuit simulation based on the charge-sheet model. The current equation consists of diffusion and drift components, therefore Ids is a smooth function of the applied voltages. Since the original charge-sheet model is valid only for long-channel transistors, it has been further developed to describe quarter-micron MOSFETs by introducing the lateral electric field Ey into the theory. The new model includes these field contributions self-consistently, and describes the drain current of MOSFETs from long to quarter-micron channel lengths with a single model parameter set without discontinuities in derivatives of the drain current Ids. The mobility reduction due to Ey is described by an empirical equation with physical parameter values taken from literature. Only two fitting parameters, the impurity scattering and the surface roughness scattering in the mobility equation, are added to the physical parameters. The subdiffusion lengths are also taken as fitting parameters. Though the new model reduces the number of fitting parameters totally to four, it reproduces measured Ids excellently for MOSFETs with all channel lengths. The model has been included in the parameter extraction program JANUS, which extracts model parameters automatically. The algorithm for parameter extraction is summarized.