We theoretically study the performance limits of current-gain cutoff frequency, fT, for the HEMTs with InAs or In0.70Ga0.30As middle layers in the multi-quantum-well (MQW) channels by means of the quantum-corrected Monte Carlo (MC) method. We calculate the distribution of the delay time along the channel, τ(x), and define the effective gate length, Lg,eff, as the corresponding length to τ(x). By extrapolating Lg,eff to Lg = 0 nm, we estimate the lower limit of Lg,eff, Lg(0),eff. Then we estimate the performance limit of fT, fT(0), by extrapolating fT to Lg,eff(0). The estimated fT(0) are about 3.6 and 3.7 THz for the HEMTs with InAs middle layers of 5 and 8 nm in thickness, and about 3.0 THz for the HEMT with In0.70Ga0.30As middle layer of 8 nm in thickness, respectively. The higher fT(0) in the HEMTs with InAs middle layers are attributed to the increased average electron velocity, υd, in the channel. These results indicate the superior potential of the HEMTs using InAs in the channels. The HEMT with InAs middle layer of 8 nm in thickness shows the highest fT on condition of the same Lg because of its highest υd. However, the increased total channel thickness results in the longer Lg,eff(0), which leads to the restriction of fT(0). Therefore, in order to increase fT(0), it is essential to make Lg,eff short in addition to making υd high. Our results strongly encourage in making an effort to develop the HEMTs that operate in the terahertz region.

E-band low-noise amplifier (LNA) monolithic millimeter-wave integrated circuits (MMICs) were developed using pseudomorphic In0.75Ga0.25As/In0.52Al0.48As high electron mobility transistors (HEMTs) with a gate length of 50 nm. The nanogate HEMTs demonstrated a maximum oscillation frequency (fmax) of 550 GHz and a current-gain cutoff frequency (fT) of 450 GHz at room temperature, which is first experimental demonstration that fmax as high as 550 GHz are achievable with the improved one-step-recessed gate procedure. Furthermore, using a three-stage LNA-MMIC with 50-nm-gate InGaAs/InAlAs HEMTs, we achieved a minimum noise figure of 2.3 dB with an associated gain of 20.6 dB at 79 GHz.

In this letter, the fabrication of a compact and high performance semi-lumped coplanar waveguide low-pass filter (CPW-LPF) on high resistivity silicon (HRS) substrate at millimeter wave is proposed. The design procedure and the equivalent circuit of the proposed semi-lumped CPW-LPF is discussed. The filter structure of is very simple but its performances is fairly good. This designed filter at cutoff frequency fc of 31 GHz has very good measured characteristics including the low insertion loss, sharp rejection and low group delay, due to the reduced substrate loss of HRS. Experimental results of the fabricated filter show a good agreement with the predicted results.

As a review of the InP HEMT technology and its applications to logic ICs, the two-step-recess gate structure, which is now widely used in high-performance InP HEMTs, and its application to optoelectronic ICs are described. This paper also covers the topic of the gate delay analysis that reveals that the parasitic delay becomes the primary cause of the gate delay in sub-100-nm gate regime. For future challenge for logic applications, ways to reduce the off-state transistor current is also discussed.

A novel fabrication technology for lateral scale-down of sub-100-nm-gate InP-based HEMTs is presented. The fabricated device, whose structure features a reduced distance between the gate and ohmic metals of less than 100 nm, exhibits low ohmic resistances and improved DC and RF characteristics with good uniformity across a wafer. A fabricated 130-nm-gate lattice-matched InAlAs/InGaAs HEMT exhibits an extrinsic transconductance of 1.3 S/mm. This is 25% increase compared to that of a HEMT fabricated with our conventional process, which is explained by the reduction of RS. The average current-gain-cutoff-frequency (fT) of 261 GHz was obtained with a small deviation of 9.0 GHz. Uniform characteristics with high yield were also confirmed for HEMTs with shorter gates. The average fT of 290 GHz with a standard deviation of 9.3 GHz was obtained for 55-nm-gate HEMTs. The developed fabrication technology is promising for improving the electrical characteristics of sub-100-nm-gate InP-based HEMTs and for their integration.

This letter presents a novel two-dimensional (2-D) defected ground array (DGA) for planar circuits, which has horizontal and vertical periodicities of defect structure. The defect unit cell of DGA is composed of a Sierpinski carpet structure to improve the effective inductance. Measurements show that the proposed DGA provides steeper cutoff characteristics, lower cutoff frequency, and higher slow-wave factors than the conventional periodic defected ground structure in the same occupied surface.

Cutoff frequencies and the modal fields in hollow conducting waveguides of arbitrary cross section are frequently calculated by the method of solving integral equations. This paper presents some improvements for the method by the integral equations. The improved method can calculate the cutoff frequencies and the modal fields only by using the real number, and this method can remove extraneous roots when calculating the cutoff frequencies. The former method calculates the cutoff frequency and the fields only at the cutoff frequency, but the improved method can calculate the fields at arbitrary phase constants.

We fabricated 50-nm-gate InAlAs/InGaAs high electron mobility transistors (HEMTs) lattice-matched to InP substrates by using a conventional process under low temperatures, below 300C, to prevent fluorine contamination and suppress possible diffusion of the Si-δ-doped sheet in the electron-supply layer, and measured the DC and RF performance of the transistors. The DC measurement showed that the maximum transconductance gm of a 50-nm-gate HEMT is about 0.91 S/mm. The cutoff frequency fT of our 50-nm-gate HEMT is 362 GHz, which is much higher than the values reported for previous 50-nm-gate lattice-matched HEMTs. The excellent RF performance of our HEMTs results from a shortening of the lateral extended range of charge control by the drain field, and this may have been achieved because the low-temperature fabrication process suppressed degradation of epitaxial structure.

A selectively grown Si1-xGex base heterojunction bipolar transistor (HBT) was fabricated, and effects of Ge and B profiles on the device performance were investigated. Since no obvious leakage current was observed, it is shown that good crystallinity of Si1-xGex was achieved by using a UHV/CVD system with high-pressure H2 pre-cleaning of the substrate. Very high current gain of 29,000 was obtained in an HBT with a uniform Ge profile by both increasing electron injection from the emitter to the base and reducing band gap energy in the base. Since the Early voltage is affected by the grading of Ge content in the base, the HBT with the graded Ge profile provides very high Early voltage. However, the breakdown voltage is degraded by increasing Ge content because of reducing bandgap energy and changing dopant profile. To increase the cutoff frequency, dopant diffusion must be suppressed, and carrier acceleration by the internal drift field with the graded Ge profile has an additional effect. By doing them, an extremely high cutoff frequency of 130 GHz was obtained in HBT with graded Ge profiles.

SiGe HBTs with doping level inversion, that is, a higher dopant concentration in the base than in the emitter, are realized based on the double-polysilicon self-aligned transistor scheme by means of selective epitaxy performed in a production CVD reactor. The effects of the Ge profile in the base on the transistor performance are explored. The fabricated HBT with a 12-27% graded Ge profile demonstrates a maximum cutoff frequency of 88 GHz, a maximum oscillation frequency of 65 GHz, and an ECL gate delay time of 13.8 ps.

This paper reports on a high-speed silicon bipolar transistor with an fT and fMAX of over 40 GHz, we call it the Advanced Boro-silicated-glass Self-Aligned (A-BSA) transistor. In basic BSA technology, a CVD-BSG film is used not only as a diffusion source to form the intrinsic base and the link base regions but also as a sidewall spacer between the emitter and the base polysilicon electrodes. An A-BSA transistor offers three advancements to this technology: (1) a graded collector profile underneath the intrinsic base region to suppress the Kirk effect; (2) an optimized design of the link base region to prevent the frade-off effect between fT and base resistance; and (3) a newly developed buried emitter electrode structure, consisting of an N++-polysilicon layer, a platinum silicide layer, and a CVD tungsten plug, to prevent the emitter plug effect. Furthermore, our transistor uses a BPSG filled trench isolation to reduce parasitic capacitance and improve circuit performance. In this paper, we describe device design, process technology and characterization of the A-BSA transistor, with it we have performed several application ICs, operating at 10Gb/s and above. The A-BSA transistor achieved an fT of 41 GHz and an fMAX of 44 GHz under optimized conditions.

Considered is the theory of several dielectric waveguide phenomena for which the vector nature of the electromagnetic field is essential. These phenomena are the following rotation of the plane of polarization in chiral and twisted waveguides, Bragg's reflection in a twisted waveguide in a narrow frequency band, and excitation of a waveguide at a near-cutoff frequency.

This paper describes IC-oriented high-performance AlGaAs/GaAs heterojunction bipolar transistors that were fabricated to demonstrate their great potential in applications to high-speed integrated circuits. A collector structure of ballistic collection transistors with a launcher (LBCTs) shortens the intrinsic delay time of the transistors. A novel and simple self-aligned fabrication process, which features an base-metal-overlaid structure (BMO), reduces emitter- and base-resistances and collector capacitance. The combination of the thin-collector LBCT layer structure and the BMO self-alignment technology raises the average value of cutoff frequency, fT, to 160 GHz with a standard deviation as small as 4.3 GHz. By modifying collector thickness and using Pt/Ti/Pt/Au as the base ohmic contact metal in BMO-LBCTs, the maximum oscillation frequency, fmax, reaches 148 GHz with a 114 GHz fT. A 2:1 multiplexer with retiming D-type flip-flops (DFFs) at input/output stages fabricated on a wafer with the thin-collector LBCT structure operates at 19 Gbit/s. A monolithic preamplifier fabricated on the same wafer has a transimpedance of 52 dBΩ with a 3-dB-down bandwidth of 18.5 GHz and a gain S21 OF 21 dB with a 3-dB-down bandwidth of 19 GHz. Finally, a 40 Gbit/s selector IC and a 50 GHz dynamic frequency divider that were successfully fabricated using the 148-GHz fmax technologies are described.

We discuss delay times derived from the current gain cutoff frequency of a heterostructure field effect transistor and describe three types of novel channel structures for millimeter-wave InP-based HFETs. The first structure discussed is a lattice-matched InGaAs HEMT with high state-of-the art performance. The second structure is an InAs-inserted InGaAs HEMT which harnesses the superior transport properties of InAs. Fabricated devices show high electron mobility of 12,800 cm2/Vs and high transconductance over 1.4 S/mm for a 0.6-µm-gate length. The effective saturation velocity in the device derived from the current gain cutoff frequency in 3.0107 cm/s. The third one is an InGaAs/InP double-channel HFET that utilizes the superior transport properties of InP at a high electric field. Fabricated double-channel devices show kink-free characteristics, high carrier density of 4.51012 cm-2 and high transconductance of 1.3 S/mm for a 0.6-µm-gate length. The estimated effective saturation velocity in these devices is 4.2107 cm/s. Also included is a discussion of the current gain cutoff frequency of ultra-short channel devices.