Power line communication (PLC) provides a flexible-access, wide-distribution, and low-cost communication solution for distribution network services. However, the PLC self-organizing networking in distribution network faces several challenges such as diversified data transmission requirements guarantee, the contradiction between long-term constraints and short-term optimization, and the uncertainty of global information. To address these challenges, we propose a backpressure learning-based data transmission reliability-aware self-organizing networking algorithm to minimize the weighted sum of node data backlogs under the long-term transmission reliability constraint. Specifically, the minimization problem is transformed by the Lyapunov optimization and backpressure algorithm. Finally, we propose a backpressure and data transmission reliability-aware state-action-reward-state-action (SARSA)-based self-organizing networking strategy to realize the PLC networking optimization. Simulation results demonstrate that the proposed algorithm has superior performances of data backlogs and transmission reliability.

To establish seamless and highly robust content distribution, we proposed the new concept of Inter-Stream Forward Error Correction (FEC), an efficient data recovery method leveraging several video streams. Our previous research showed that Inter-Stream FEC had significant recovery capability compared with the conventional FEC method under ideal modeling conditions and assumptions. In this paper, we design the Inter-Stream FEC architecture in detail with a view to practical application. The functional requirements for practical feasibility are investigated, such as simplicity and flexibility. Further, the investigation clarifies a challenging problem: the increase in processing delay created by the asynchronous arrival of packets. To solve this problem, we propose a pragmatic parity stream construction method. We implement and evaluate experimentally a prototype system with Inter-Stream FEC. The results demonstrate that the proposed system could achieve high recovery performance in our experimental environment.

We propose an optimization method for power distribution network that explicitly deals with timing. We have found and focused on the facts that decoupling capacitance (decap) does not necessarily improve gate delay depending on the switching timing within a cycle and that power wire expansion may locally degrade the voltage. To resolve the above facts, we devised an efficient sensitivity calculation of timing to decap size and power wire width for guiding optimization. The proposed method, which is based on statistical noise modeling and timing analysis, accelerates sensitivity calculation with an approximation and adjoint sensitivity analysis. Experimental results show that decap allocation based on the sensitivity analysis efficiently minimizes the worst-case circuit delay within a given decap budget. Compared to the maximum decap placement, the delay improvement due to decap increases by 3.13% even while the total amount of decaps is reduced to 40%. The wire sizing with the proposed method also efficiently reduces required wire resource necessary to attain the same circuit delay by 11.5%.

With the progress of process technology in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the on-chip decoupling capacitance optimization that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the on-chip decoupling capacitance area will reduce the chip area and, therefore, manufacturing costs. Hence, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the total on-chip decoupling capacitance area. The proposed algorithm uses the idea of the network algorithm where the path which has the most influence on voltage drop is found. Voltage drop is improved by adding the on-chip capacitance to the node on the path. The proposed algorithm is efficient and effectively adds the on-chip capacitance to the greatest influence on the voltage drop. Experimental results demonstrate that, with the proposed algorithm, real size power/ground network could be optimized in just a few minutes which are quite practical. Compared with the conventional algorithm, we confirmed that the total on-chip decoupling capacitance area of the power/ground network was reducible by about 4050%.

With the process technological progress in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the power/ground design that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the power/ground total wiring area and the number of layers will reduce manufacturing and designing costs. So, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the power/ground total wiring area. The proposed algorithm uses the idea of a network algorithm [1] where the edge which has the most influence on voltage drop is found. Voltage drop is improved by changing the resistance of the edge. The proposed algorithm is efficient and effectively updates the edge with the greatest influence on the voltage drop. From experimental results, compared with the conventional algorithm, we confirmed that the total wiring area of the power/ground was reducible by about 1/3. Also, the experimental data shows that the proposed algorithm satisfies the voltage drop constraint in the data whereas the conventional algorithm cannot.

A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The maximum and minimum capacitances are also calculated using average and variance estimation. Calculation times are linear time-complexity, too. The proposed tool facilitates to build an accurate macro model of an LSI.

This paper provides an investigation of power distribution network (PDN) performance by a full-wave prediction tool and by experimental measurements. A set of six real boards characterized by increasing complexity is considered in order to establish a solid base for behaviour understanding of printed circuit boards. How the growing complexity impacts on the board performance is investigated by measurements and by simulations. Strengths and weakness of PDN modeling by the full-wave software tool Microwave Studio are highlighted and discussed.

Electrical modeling for surface-mount passive components is proposed. In order to accurately capture parasitic inductance, the proposed 2-port model accounts for surrounding ground layer configurations of the print circuit board (PCB) on which the component is mounted. Our model retains conventional modeling paradigm in which component suppliers provide their customers with simulation models characterized independently of the customers' PCB. We also present necessary corrections that compensate magnetic coupling between the separated models. Impedance and its anti-resonant frequency of two power distribution networks are experimentally analyzed being non-separated modeling as the reference. The proposed model achieved very good match with the reference result reducing 7-34% error of the conventional model to about 2%.

In this paper, we present and verify a new chip-package co-modeling and simulation approach for a low-noise chip-package hierarchical power distribution network (PDN) design. It is based on a hierarchical modeling to combine distributed circuit models at both chip-level PDN and package-level PDN. In particular, it includes all on- and off-chip parasitic circuit elements in the hierarchical PDN with a special consideration on on-chip decoupling capacitor design and placement inside chip. The proposed hierarchical PDN model was successfully validated with good correlations and subsequent analysis to a series of Z11 and Z21 PDN impedance measurements with a frequency range from 1 MHz to 3 GHz. Using the proposed model, we can analyze and estimate the performance of the chip-package hierarchical PDN as well as can predict the effect of high frequency electromagnetic interactions between the chip-level PDN and the package-level PDN. Furthermore, we can precisely anticipate PDN resonance frequencies, noise generation sources, and noise propagation paths through the multiple levels in the hierarchical PDN.

Stochastic approaches for effective power distribution network optimization are proposed. Considering node voltages obtained using dynamic voltage drop analysis as sample variables, multi-variate regression is conducted to optimize clock timing metrics, such as clock skew or jitter. Aggregate correlation coefficient (ACC) which quantifies connectivity between different chip regions is defined in order to find a possible insufficiency in wire connections of a power distribution network. Based on the ACC, we also propose a procedure using linear regression to find the most effective region for improving clock timing metrics. By using the proposed procedure, effective fixing point were obtained two orders faster than by using brute force circuit simulation.

The evolution of VLSI chips towards larger die size, smaller feature size and faster clock speed makes the clock distribution an increasingly important issue. In this paper, we propose a new clock distribution network (CDN), namely Variant X-Tree, based on the idea of X-Architecture proposed recently for efficient wiring within VLSI chips. The Variant X-Tree CDN keeps the nice properties of equal-clock-path and symmetric structure of the typical H-Tree CDN, but results in both a lower maximal clock delay and a lower clock skew than its H-Tree counterpart, as verified by an extensive simulation study that incorporates simultaneously the effects of process variations and on-chip inductance. We also propose a closed-form statistical models for evaluating the skew and delay of the Variant X-Tree CDN. The comparison between the theoretical results and the simulation results indicates that the proposed statistical models can be used to efficiently and rapidly evaluate the performance of the variant X-Tree CDNs.

In this paper, we propose two methods to estimate clock jitter caused by power supply noise in a LSI (Large-Scale Integrated circuit). One of the methods enables estimation of clock jitter at the initial design stage before floor-planning. The other method reduces simulation time of clock distribution network to analyze clock jitter at the design verification stage after place-and-route of the chip. For an example design, the relative difference between clock jitter estimated at the initial design stage and that of the design verification stage is 23%. The example result also shows that the proposed method for the verification stage is about 24 times faster than the conventional one to analyze clock jitter.

Fast and accurate power bus designer (FAPUD) for multi-layers high-speed digital boards is the power supply network design tool for accurate and precise high speed board. FAPUD is constructed based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching in can be carried out because the I/O switching effect on a power supply noise can estimate for the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.

With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We perform a case study work that evaluates relation between decoupling capacitance position and noise suppression effect, and we reveal that placing decoupling capacitance close to current load is necessary for noise reduction. We experimentally show that impact of on-chip inductance becomes small when on-chip decoupling capacitance is well placed according to local power consumption. We also examine influences of grid pitch, wire area, and spacing between paired power and ground wires on power supply noise. When effect of on-chip inductance on power/ground noise is significant, minification of grid pitch is more efficient than increase in wire area, and small spacing reduces power noise as we expected.

In this paper, we propose multicast technique in order to reduce the required network bandwidth by n times, by merging the adjacent multicasts depending on the number of HENs (Head-End-Nodes) n that request the same video. Allowing new clients to immediately join an existing multicast through patching improves the efficiency of the multicast and offers services without any initial latency. A client might have to download data through two channels simultaneously, one for multicast and the other for patching. Each video stream is divided into blocks which are the same size of multicast grouping interval Im. Blocks then are evenly distributed into different HENs according to their popularity and the order of requests. Only when the playback time exceeds the amount of cached video data, server generates new multicast channel. Since the interval of multicast can be dynamically expanded according to the popularity of videos, it can be reduced the server's workload and the network bandwidth. We adopt the cache replacement strategy as LFU (Least-Frequently-Used) for popular videos, LRU (Least-Recently-Used) for unpopular videos, and the method for replacing the first block of video last to reduce end-to-end latency. We perform simulations to compare its performance with that of conventional multicast. From simulation results, we confirm that the proposed multicast technique offers substantially better performance.

Content Distribution Networks (CDNs) are highly advanced architectures for networks on the Internet, providing low latency, scalability, fault tolerance, and load balancing. One of the most important issues to realize these advantages of CDNs is dynamic content allocation to deal with temporal load fluctuation, which provides mirroring of content files in order to distribute user accesses. Since user accesses for content files change over time, the content files need to be reallocated appropriately. In this paper, we propose a cost-effective content migration method called the Step-by-Step (SxS) Migration Algorithm for CDNs, which can dynamically relocate content files while reducing transmission cost. We show that our method maintains sufficient performance while reducing cost in comparison to the conventional shortest-path migration method. Furthermore, we present six life cycle models of content to consider realistic traffic patterns in our simulation experiments. Finally, we evaluate the effectiveness of our SxS Migration Algorithm for dynamic content reconfiguration across time.

An efficient pad assignment methodology to minimize voltage drop on a power distribution network is proposed. A combination of successive pad assignment (SPA) with incremental matrix inversion (IMI) determines both location and number of power supply pads to satisfy drop voltage constraint. The SPA creates an equivalent resistance matrix which preserves both pad candidates and power consumption points as external ports so that topological modification due to connection or disconnection between voltage sources and candidate pads is consistently represented. By reusing sub-matrices of the equivalent matrix, the SPA greedily searches the next pad location that minimizes the worst drop voltage. Each time a candidate pad is added, the IMI reduces computational complexity significantly. Experimental results including a 400 pad problem show that the proposed procedures efficiently enumerate pad order in a practical time.

This letter presents a novel method to design a power distribution network with highly accurate impedance characteristic. Based on the PBEC (path-based equivalent circuit) model and the network synthesis, the proposed design method exploits simple arithmetic expressions to calculate the electrical parameters of a power distribution network. It directly calculates and determines the size of on-chip decoupling capacitors, the size and location of off-chip decoupling capacitors, and the effective inductances of the package power bus. To evaluate the accuracy of the proposed method, it was applied to a test board with size of 12.5 cm 12.5 cm and with plane-to-plane distance of 200 µm. The proposed method successfully designed a power distribution network keeping its impedance characteristic under 1 Ω with frequency range of 100 kHz-1 GHz. The proposed design method requires negligible computation when compared with conventional PEEC (partial elements equivalent circuit) model-based design approaches, but the simulation results of both methods are almost identical. Consequently, the proposed method enables simple, fast and accurate design of power-distribution networks, which gives economic and practical solutions for commercial tools.

In content distribution networks (CDNs), the content routing which directs user requests to an adequate server from the viewpoint of improvement of latency for obtaining contents is one of the most important technical issues. Several information, e.g. server load or network delay, can be used for content routing. Network support, e.g. active network, enables a router to select an adequate server by using these information. In the paper, we investigate a server selection policy of a network support approach from the viewpoint of which information to be used for effective server selection. We propose a server selection policy using RTT information measured at a router. Simulation results show that our proposed server selection policy in content routing selects a good server under both conditions where server latency and network delay is a dominant element of user response time. Furthermore, we also investigate about location of routers with network support bringing good performance for our proposed scheme.

Fiber optic subcarrier transmission system using coherence multiplexing techniques for broad-band distribution networks is proposed. This system makes it possible to improve the laser linewidth requirement and also to eliminate the effect of intermodulation distortion (IMD) which is serious problem in subcarrier multiplexed (SCM) system. In the proposed system, the frequency difference, fo, between the reference light and the signal light makes it possible to generate the broadand FM signal after photodetecting. Thus, an increase in the modulation index provides a corresponding increase in receiver sensitivity. We analyze the fundamental performance of the proposed system and derive the signal-to-noise ratio (SNR) at the output of FM demodulator by taking the threshold effect and spike noise into account. The proposed system can achieve the total capacity in excess of 10 GHz, and thus it is attractive for multichannel broad-band distribution networks.