This paper presents examination result of possibility for automatic unclear region detection in the CAD system for colorectal tumor with real time endoscopic video image. We confirmed that it is possible to realize the CAD system with navigation function of clear region which consists of unclear region detection by YOLO2 and classification by AlexNet and SVMs on customizable embedded DSP cores. Moreover, we confirmed the real time CAD system can be constructed by a low power ASIC using customizable embedded DSP cores.

We propose online feedback path modeling with a pre-inverse type active noise control (PIANC) system to track the fluctuation stably in the feedback path. The conventional active noise control (ANC) system with online feedback path modeling (FBPM) filter bases filtered-x least mean square (FxLMS) algorithm. In the FxLMS algorithm, the error of FBPM influences a control filter, which generates an anti-noise, and secondary path modeling (SPM) filter. The control filter diverges when the error is too large. Therefore, it is difficult for the FxLMS algorithm to track the feedback path without divergence. On the other hand, the proposed approach converges stably because the FBPM filter's error does not influence a control filter on the PIANC system. Thus, the proposed method can reduce noise while tracking the feedback path. This paper verified the effectiveness of the proposed method by convergence analysis, computer simulation, and implementation of a digital signal processor.

In this paper, we present a hardware implementation of a colorectal cancer diagnosis support system using a colorectal endoscopic video image on customizable embedded DSP. In an endoscopic video image, color shift, blurring or reflection of light occurs in a lesion area, which affects the discrimination result by a computer. Therefore, in order to identify lesions with high robustness and stable classification to these images specific to video frame, we implement a computer-aided diagnosis (CAD) system for colorectal endoscopic images with Narrow Band Imaging (NBI) magnification with the Convolutional Neural Network (CNN) feature and Support Vector Machine (SVM) classification. Since CNN and SVM need to perform many multiplication and accumulation (MAC) operations, we implement the proposed hardware system on a customizable embedded DSP, which can realize at high speed MAC operations and parallel processing with Very Long Instruction Word (VLIW). Before implementing to the customizable embedded DSP, we profile and analyze processing cycles of the CAD system and optimize the bottlenecks. We show the effectiveness of the real-time diagnosis support system on the embedded system for endoscopic video images. The prototyped system demonstrated real-time processing on video frame rate (over 30fps @ 200MHz) and more than 90% accuracy.

We propose an auxiliary-noise power-scheduling method for a pre-inverse active noise control (PIANC) system. Conventional methods cannot reduce the power of auxiliary-noise due to the use of the filtered-x least mean square (FxLMS) algorithm. We developed our power-scheduling method for a PIANC system to solve this problem. Since a PIANC system uses a delayed input signal for a control filter, the proposed method delivers stability even if the acoustic path fluctuates. The proposed method also controls the gain of the auxiliary-noise based on the secondary-path-modeling state. The proposed method determines this state by the variation in the power of the secondary-path-modeling-error signal. Thus, the proposed method changes the power-scheduling of the auxiliary-noise. When the adaptive algorithm does not sufficiently converge, the proposed method injects auxiliary-noise. However, auxiliary-noise stops when the adaptive algorithm sufficiently converges. Therefore, the proposed method improves noise reduction performance.

Adaptive Volterra filters (AVFs) are usually used to identify nonlinear systems, such as loudspeaker systems, and ordinary adaptive algorithms can be used to update the filter coefficients of AVFs. However, AVFs require huge computational complexity even if the order of the AVF is constrained to the second order. Improving calculation efficiency is therefore an important issue for the real-time implementation of AVFs. In this paper, we propose a novel sub-band AVF with high calculation efficiency for second-order AVFs. The proposed sub-band AVF consists of four parts: input signal transformation for a single sub-band AVF, tap length determination to improve calculation efficiency, switching the number of sub-bands while maintaining the estimation accuracy, and an automatic search for an appropriate number of sub-bands. The proposed sub-band AVF can improve calculation efficiency for which the dominant nonlinear components are concentrated in any frequency band, such as loudspeakers. A simulation result demonstrates that the proposed sub-band AVF can realize higher estimation accuracy than conventional efficient AVFs.

We describe a field experiment of flexible modulation format adaptation on a real-time 400Gbit/s/ch DSP-LSI. This real-time DSP-LSI features OSNR estimation, practical simplified back propagation, and high gain soft-decision forward error correction. With these techniques, we have successfully demonstrated modulation format allocation and transmission of 56-channel 400Gbit/s-2SC-PDM-16QAM and 200Gbit/s-2SC-PDM-QPSK signals in 216km and 3246km standard single mode fiber, respectively.

Reconfigurable architectures have emerged as an optimal choice for the hardware realization of digital signal processing (DSP) algorithms. Reconfigurable architecture is either fine-grained or coarse-grained depending on the granularity of reconfiguration used. The flexibility offered by fine-grained devices such as field programmable gate array (FPGA) comes at a significant cost of huge routing area, power consumption and speed overheads. To overcome these issues, several coarse-grained reconfigurable architectures have been proposed. In this paper, a scalable and hybrid dynamically reconfigurable architecture, HyDRA, is proposed for efficient hardware realization of computation intensive DSP algorithms. The proposed architecture is greatly influenced by reported VLSI architectures of a variety of DSP algorithms. It is designed using parameterized VHDL model which allows experimenting with a variety of design features by simply modifying some constants. The proposed architecture with 8×8 processing element array is synthesized using UMC 0.25µm and LF 150nm CMOS technologies respectively. For quantitative evaluation, the architecture is also realized using Xilinx Virtex-7 FPGA. The area and timing results are presented to provide an estimate of each block of the architecture. DSP algorithms such as 32-tap finite impulse response (FIR) filters, 16-point radix-2 single path delay feedback (R2SDF) fast fourier transform (FFT) and R2SDF discrete cosine transform (DCT) are mapped and routed on the proposed architecture.

In this paper, we propose a 3rd-order nonlinear IIR filter for compensating nonlinear distortions of loudspeaker systems. Nonlinear distortions are common around the lowest resonance frequency for electrodynamic loudspeaker systems. One interesting approach to compensating nonlinear distortions is to employ a mirror filter. The mirror filter is derived from the nonlinear differential equation for loudspeaker systems. The nonlinear parameters of a loudspeaker system, which include the force factor, stiffness, and so forth, depend on the displacement of the diaphragm. The conventional filter structure, which is called the 2nd-order nonlinear IIR filter that originates the mirror filter, cannot reduce nonlinear distortions at high frequencies because it does not take into account the nonlinearity of the self-inductance of loudspeaker systems. To deal with this problem, the proposed filter takes into account the nonlinearity of the self-inductance and has a 3rd-order nonlinear IIR filter structure. Hence, this filter can reduce nonlinear distortions at high frequencies while maintaining a lower computational complexity than that of a Volterra filter-based compensator. Experimental results demonstrate that the proposed filter outperforms the conventional filter by more than 2dB for 2nd-order nonlinear distortions at high frequencies.

In this paper, we propose a parameter estimation method using Volterra kernels for the nonlinear IIR filters, which are used for the linearization of closed-box loudspeaker systems. The nonlinear IIR filter, which originates from a mirror filter, employs nonlinear parameters of the loudspeaker system. Hence, it is very important to realize an appropriate estimation method for the nonlinear parameters to increase the compensation ability of nonlinear distortions. However, it is difficult to obtain exact nonlinear parameters using the conventional parameter estimation method for nonlinear IIR filter, which uses the displacement characteristic of the diaphragm. The conventional method has two problems. First, it requires the displacement characteristic of the diaphragm but it is difficult to measure such tiny displacements. Moreover, a laser displacement gauge is required as an extra measurement instrument. Second, it has a limitation in the excitation signal used to measure the displacement of the diaphragm. On the other hand, in the proposed estimation method for nonlinear IIR filter, the parameters are updated using simulated annealing (SA) according to the cost function that represents the amount of compensation and these procedures are repeated until a given iteration count. The amount of compensation is calculated through computer simulation in which Volterra kernels of a target loudspeaker system is utilized as the loudspeaker model and then the loudspeaker model is compensated by the nonlinear IIR filter with the present parameters. Hence, the proposed method requires only an ordinary microphone and can utilize any excitation signal to estimate the nonlinear parameters. Some experimental results demonstrate that the proposed method can estimate the parameters more accurately than the conventional estimation method.

Earlier attempts to deploy two units of parametric loudspeakers have shown encouraging results in improving the accuracy of spatial audio reproductions. As compared to a pair of conventional loudspeakers, this improvement is mainly a result of being free of crosstalk due to the sharp directivity of the parametric loudspeaker. By replacing the normal parametric loudspeaker with the steerable parametric loudspeaker, a flexible sweet spot can be created that tolerates head movements of the listener. However, spatial aliasing effects of the primary frequency waves are always observed in the steerable parametric loudspeaker. We are motivated to make use of the spatial aliasing effects to create two sound beams from one unit of the steerable parametric loudspeaker. Hence, a reduction of power consumption and physical size can be achieved by cutting down the number of loudspeakers used in an audio system. By introducing a new parameter, namely the relative steering angle, we propose a stereophonic beamsteering method that can control the amplitude difference corresponding to the interaural level difference (ILD) between two sound beams. Currently, this proposed method does not support the reproduction of interaural time differences (ITD).

This work presents a four-channel headset achieving a 5.1-channel-like hearing experience using a low-complexity head-related transfer function (HRTF) model and a simplified reverberator. The proposed down-mixing architecture enhances the sound localization capability of a headset using the HRTF and by simulating multiple sound reflections in a room using Moorer's reverberator. Since the HRTF has large memory and computation requirements, the common-acoustical-pole and zero (CAPZ) model can be used to reshape the lower-order HRTF model. From a power consumption viewpoint, the CAPZ model reduces computation complexity by approximately 40%. The subjective listening tests in this study shows that the proposed four-channel headset performs much better than stereo headphones. On the other hand, the four-channel headset that can be implemented by off-the-shelf components preserves the privacy with low cost.

This paper presents an efficient approach for logarithmic and anti-logarithmic converters which can be used in the arithmetic unit of hybrid number system processors and logarithm/exponent function generators in DSP applications. By employing the novel quasi-symmetrical difference method with only the simple shift-add logic and the look-up table, the proposed approach can reduce the hardware area and improve the conversion speed significantly while achieve similar accuracy compared with the previous methods. The implementation results in both FPGA and 0.18-µm CMOS technology are also presented and discussed.

In this paper, an improved hybrid LUT-based architecture for low-error and efficient fixed-width squarer circuits is presented in which LUT-based and conventional logic circuits are employed together to achieve the good trade-off between hardware complexity and performance. By exploiting the mathematical identities and hybrid architecture, the mean error and mean squarer error of the proposed squarer are reduced by up to 40%, compared with the best previous method presented in literature. Moreover, the proposed method can improve the speed and reduce the area of the squarer circuit. The implementation and chip measurement results in 0.18-µm CMOS technology are also presented and discussed.

We propose and demonstrate a simple and novel technique to accelerate the carrier injection/depletion processes in an RSOA by applying instantaneous injection/depletion currents at the transition edges of the modulation signal to force the carrier density to respond at a high speed and, as a result, to increase its modulation speed. We theoretically and experimentally show that, by using the proposed technique, it is possible to obtain 5 Gbit/s optical BPSK signal from an RSOA having a modulation bandwidth of only 0.9 GHz.

We present an economical and fault-tolerant load balancing strategy (EFTLBS) based on an operator replication mechanism and a load shedding method, that fully utilizes the network resources to realize continuous and highly-available data stream processing without dynamic operator migration over wide area networks. In this paper, we first design an economical operator distribution (EOD) plan based on a bin-packing model under the constraints of each stream bandwidth as well as each server's CPU capacity. Next, we devise super-operator (SO) that load balances multi-degree operator replicas. Moreover, for improving the fault-tolerance of the system, we color the SOs based on a coloring bin-packing (CBP) model that assigns peer operator replicas to different servers. To minimize the effects of input rate bursts upon the system, we take advantage of a load shedding method while keeping the QoS guarantees made by the system based on the SO scheme and the CBP model. Finally, we substantiate the utility of our work through experiments on ns-3.

Emerging video surveillance technologies are based on foreground detection to achieve event detection automatically. Integration foreground detection with a modern multi-camera surveillance system can significantly increase the surveillance efficiency. The foreground detection often leads to high computational load and increases the cost of surveillance system when a mass deployment of end cameras is needed. This paper proposes a DSP-based foreground detection algorithm. Our algorithm incorporates a temporal data correlation predictor (TDCP) which can exhibit the correlation of data and reduce computation based on this correlation. With the DSP-oriented foreground detection, an adaptive frame rate control is developed as a low cost solution for multi-camera surveillance system. The adaptive frame rate control automatically detects the computational load of foreground detection on multiple video sources and adaptively tunes the TDCP to meet the real-time specification. Therefore, no additional hardware cost is required when the number of deployed cameras is increased. Our method has been validated on a demonstration platform. Performance can achieve real-time CIF frame processing for a 16-camera surveillance system by single-DSP chip. Quantitative evaluation demonstrates that our solution provides satisfied detection rate, while significantly reducing the hardware cost.

We propose an active noise control (ANC) system for reducing periodic noise generated in a high magnetic field such as noise generated from magnetic resonance imaging (MRI) devices (MR noise). The proposed ANC system utilizes optical microphones and piezoelectric loudspeakers, because specific acoustic equipment is required to overcome the high-field problem, and consists of a head-mounted structure to control noise near the user's ears and to compensate for the low output of the piezoelectric loudspeaker. Moreover, internal model control (IMC)-based feedback ANC is employed because the MR noise includes some periodic components and is predictable. Our experimental results demonstrate that the proposed ANC system (head-mounted structure) can significantly reduce MR noise by approximately 30 dB in a high field in an actual MRI room even if the imaging mode changes frequently.

The problem of estimating the nominal angles and angular spreads of multiple coherently distributed (CD) sources in a symmetric uniform linear array (ULA) is considered. Based on structure of the subarrays consisting of two opposite sensors relative to the center of a ULA and the rank reduction (RARE) concept, the proposed algorithm is able to estimate the nominal angles without any angular signal density model assumptions of the sources. Using the estimated nominal angles, the angular spread of each source is then obtained using a one-dimensional (1-D) distributed source parameter estimator (DSPE).

This paper presents a low complexity partially folded architecture of transposed FIR filter and cubic B-spline interpolator for ATSC terrestrial broadcasting systems. By using the multiplexer, the proposed FIR filter and interpolator can provide high clock frequency and low hardware complexity. A binary representation method was used for designing the high order FIR filter. Also, in order to compensate the truncation error of FIR filter outputs, a fixed-point range detection method was used. The proposed partially folded architecture was designed and implemented with 90-nm CMOS technology that had a supply voltage of 1.1 V. The implementation results show that the proposed architectures have 12% and 16% less hardware complexity than the other kinds of architecture. Also, both the filter and the interpolator operate at a clock frequency of 200 MHz and 385 MHz, respectively.

In this letter, the compensation ability of nonlinear distortions for loudspeaker systems is demonstrated using dynamic distortion measurement. Two linearization methods using a Volterra filter and a Mirror filter are compared. The conventional evaluation utilizes swept multi-sinusoidal waves. However, it is unsatisfactory because wideband signals such as those of music and voices are usually applied to loudspeaker systems. Hence, the authours use dynamic distortion measurement employing a white noise. Experimental results show that the two linearization methods can effectively reduce nonlinear distortions for wideband signals.