We developed piezoresistors with an intrinsic compensation of the offset temperature characteristics. High energy ion implantation was applied to fabricate this type of piezoresistor. The dopant profile of the buried piezoresistor resembles to that of the junction gate field effect transistor (JFET). The buried layer corresponds to a channel of JFET, and the substrate bias corresponds to the gate voltage. Owing to the independent temperature varying parameters, i.e., width of the depletion layer and carrier mobility in the channel, the drain current of the JFET has a temperature independent point at an appropriate gate source voltage. The effect was used in the new type of buried piezoresistor which has a driving point of zero temperature coefficient of resistance at an appropriate gate source voltage.

This paper describes small AlGaAs/GaAs HBT's for low-power and high-speed integrated circuits. The device fabrication is based on a new bridged base electrode technology that permits emitter width to be defined down to 1 µm. The new technology features oxygen-ion implantation for emitter-base junction isolation and zinc diffusion for extrinsic base formation. The oxygen-ion implanted emitter-base junction edge has been shown to provide a periphery recombination current much lower than that for the previous proton implanted edgs, the result being a much higher current gain particularly in small devices. The zinc diffusion offers high device yield and good uniformity in device characteristics even for a very thin (0.04 µm) base structure. An HBT with emitter dimensions of 12.4 µm2 yields an fT of 103 GHz and an fmax of 62 GHz, demonstrating that the new technology has a significant advantage in reducing the parasitic elements of small devices. Fabricated one-by-eight static frequency dividers and one-by-four/one-by-five two-modulus prescalers operate at frequencies over 10 GHz. The emitters of HBT's used in the divider are 12.4 µm2 in size, which is the smallest ever reported for AlGaAs/GaAs HBT IC's. These results indicate that the bridged base electrode technology is promising for developing a variety of high-speed HBT IC's.

We report the development of high-performance small-scale AlGaAs/GaAs collector-up heterojunction bipolar transistors (C-up HBT) with a carbon (C)-doped base layer. Oxygen-ion (O+) implantation is used to define their intrinsic emitter/base junctions and zinc (Zn)-diffusion is used to lower the resistivity of their O+-implanted extrinsic base layers. The highly resistive O+-implanted AlGaAs layer in the extrinsic emitter region sufficiently suppresses electron injection even under high-forward-bias conditions, allowing high collector current densities. The use of a C-doped base is especially effective for small-scale C-up HBT's because it suppresses the undesirable turn-on voltage shift caused by base dopant diffusion in the intrinsic area around the collector-mesa perimeter that occurs during the high-temperature Zn-diffusion process after implantation. Even in a small-scale trasistor with a 2 µm2 µm collector, a current gain of 15 is obtained. A microwave transistor with a 2 µm10 µm collector has a cutoff frequency fT of 68 GHz and a maximum oscillation frequency fmax of 102 GHz. A small-scale C-up HBT with a 2 µm2 µm collector shows a higher fmax of 110 GHz due to reduced base/collector capacitance CBC and its fmax remains above 100 GHz, even at a low collector current of 1 mA. The CBC of this device is estimated to be as low as 2.2 fF. Current gain dependence on collector size is also investigated for C-up HBT's and it is found that the base recombination current around the collector-mesa perimeter reduces the current gain.

C-V and I-V characteristics of an n-MOSFET with Si-implanted gate-SiO2 of 50 nm are analyzed by using a test device with large equal channel width and length of 100 µm, and discussed for realizing a large hysteresis window of threshold voltage. Interface trap densities change logarithmically from 31010 to 11012cm2eV1 as the Si-dose at 25 keV increases from zero to 31016cm2. Threshold-voltage changes caused by 25 keV implantaions are as high as 0.2 V. Effective mobilities (subthreshold swings) change from 600 (0.10) to 100 cm2/Vs (0.26 V/decade) as the Si-dose increases from 0 to 31016 cm2 at 25 keV, and both parameters are related with the change of interface trap densities. There is a close relationship between the hysteresis windows of gate current and threshold voltage, and the largest threshold voltage window in a low gate voltage region is obtained for the MOSFET with Si-implantation at 25 keV/31016 cm2.

The dielectric breakdown characteristics of a thin gate oxide during high-current ion implantation with an electron shower have been investigated by controlling the energy distribution of the electrons. Degradation of the oxide has also been discussed with regard to the total charge injected into the oxide during ion implantation in comparison with that of the TDDB (time dependent dielectric breakdown). Experimental results show that the high-energy and high-density electrons which concentrated in the circumference of the ion beam due to the space charge effect cause the degradation of the thin oxide. It was confirmed that eliminating the high-energy electrons by applying magnetic and electric fields lowers the electron energy at the wafer surface, thereby effectively suppressing the negative charge-up.

A fully three-dimensional simulation tool for modeling the ion implantation in arbitrarily complex three-dimensional structures is described. The calculation is based on the Monte Carlo (MC) method. For MC simulations of realistic three-dimensional structures the key problem is the CPU-time consumption which is primarily caused by two facts. (1) A large number of ion trajectories (about 107) has to be simulated to get results with reasonable low statistical noise. (2) The point location problem is very complex in the three-dimensional space. Solutions for these problems are given in this paper. To reduce the CPU-time for calculating the numerous ion trajectories a superposition method is applied. For the point location (geometry checks) different possibilities are presented. Advantages and disadvantages of the conventional intersection method and a newly introduced octree method are discussed. The octree method was found to be suited best for three-dimensional simulation. Using the octree the CPU-time required for the simulation of one ion trajectory could be reduced so that it only needs approximately the same time as the intersection method in the two-dimensional case. Additionally, the data structure of the octree simplifies the coupling of this simulation tool with topography simulators based on a cellular method. Simulation results for a three-dimensional trench structure are presented.

Self-aligned aluminum-gate MOSFET's have been successfully fabricated by employing ultraclean ion implantation technology. The use of ultra high vacuum ion implanter and the suppression of high-energy ion-beam-induced metal sputter contamination have enabled us to form ultra-shallow low-leakage pn junctions by furnace annealing at a temperature as low as 450. The fabricated aluminum-gate MOSFET's have exhibited good electrical characteristics, thus demonstrating a large potential for application to realizing ultra-high-speed integrated circuits.

The threading dislocation density and the structure of SIMOX wafers formed under different implantation conditions have been invenstigated using Secco etching, cross-sectional transmission electron microscopy and Raman spectroscopy. The breakdown voltage of the buried oxide layer has also been studied. The dislocation density is greatly affected by the dose and the wafer temperature during implantation. The SIMOX wafer implanted at 180 keV with a substoichiometric dose of 0.4 1018 O+ cm-2 at 550 and subsequently annealed at 1350 has an extremely low dislocation density on the order of 102 cm-2. The effect of the wafer temperature on the reduction of the dislocation density is discussed.

Diffusion of phosphorus impurities from a polycrystalline silicon films into a silicon substrate was investigated as a function of the mean concentration of phosphorus in a polycrystalline silicon film at the first diffusion stage. We presented that good control of the redistribution of implanted phosphorus impurities was possible by optimizing the normalized dose, which is the value: [the total dose of phosphorus impurities]/[the polycrystalline silicon film thickness], in the case of samples both with and without an arsenic doped layers. In the range where the normalized dose was less than 1.52.51020 cm-3, deeper junctions were formed in samples with an arsenic doped layer. In the range where the normalized dose was more than 1.52.51020 cm-3, however, deeper junctions were formed in samples without any arsenic doped layer rather than in samples with an arsenic doped layer. These results mean that formation of the junction in the device structure where a high concentration phosphorus doped polysilicon layer is stacked on to the high concentration arsenic layer embeded at the surface of the substrate can be restricted by optimizing the normalized dose. Moreover, a trade-off relationship between suppressing phosphorus diffusion and maintaining low contact resistance against normalized doses was also observed.

A new channel stop design for submicton local oxidation of silicon (LOCOS) isolation was presented. The n-channel stop was designed with boron implanation after forming LOCOS, while the p-channel stop was constructed with high energy phosphorus or arsenic implantation before or after forming LOCOS. These optimized channel stop designs can extend an isolation spacing to the submicron region without a decrease in junction breakdown voltage and an increase in junction leakage current. Narrow channel effects were found to be effectively suppressed by optimum channel stop design issues.

In recent years, ion implantation has become one of the key techniques in semiconductor fabrication. The annealing of the damage produced during implantation is, however, not fully understood. Ion implantation at high temperatures allows the time-resolved study of implantation-enhanced diffusion. During the process, point defects are generated by the ion implantation and consumed by recombination in the bulk as well as by diffusion to the surface and recombination there. With increasing temperatures, the recombination of point defects, which are acting as diffusion vehicles, results in reduced effective diffusion. Profiles processed above 900 show marked uphill diffusion at the surface caused by large gradients of the point defect concentrations. This uphill diffusion affirms the generally accepted pair diffusion theories. Since the point defects are in steady state even after process times which are short compared to the total process time, we are able to give a qualitative analysis of the dose dependence of the diffusion. By extensive numerical simulations, we could estimate the product of bulk recombination rate and equilibrium concentrations of self-interstitials and vacancies as well as the interface recombination velocity for the self-interstitials. The results obtained are in qualitative agreement with previous work of others. The results demonstrate, in fact, clearly the advantages of the method presented. But due to experimental problems concerning the temperature measurement, which have not been fully resolved up to now, the results have to be considered as crude estimates.