This paper describes a VLSI processor architecture designed for a back-propagation accelerator. Three techniques are used to accelerate the simulation. The first is a multi-processor approach where a neural network simulation is suitable for parallel processing. By constructing a ring network using several processors, the simulation speed is multiplied by the number of the processors. The second technique is internal parallel processing. Each processor contains 4 multipliers and 4 ALUs that all work in parallel. The third technique is pipelining. The connections of eight functional units change according to the current stage of the back-propagation algorithm. Intermediate data is sent from one functional unit to another without being stored in extra registers and data is processed in a pipeline manner. The data is in 24-bit floating point format (18-bit mantissa and 6-bit oxponent). The chip has about 88,000 gates, including microcode ROM for processor control, the processor is designed using 0.8-µm CMOS gate arrays, and the estimated performance at 40 MHz is 20 million connection updates per second (MCUPS). For a ring network with 4 processors, performance can be enhanced up to 90 MCUPS.

An autonatic layout scheme dedicated to bipolar analog modules is described. A layout model is settled in such a way that the VCC/GND line is laid out on top/bottom edge of a rectangular region, within which the whole elements are placed and interconnected. According to this simple modeling, a layout scheme can be constructed of a series of the following algorithms: First clustering is executed for partitioning a given circuit into clusters, each having connections with VCC and GND lines, and then linear ordering is applied to clusters so as to be placed in a one-dimensional array. After a relative placement of circuits elements in each cluster, a block compactor is implemented by means of packing blocks in each cluster into an idle space, and then a detailed router is conducted to attain 100% interconnection. Finally a layout compactor is invoked to pack all layout patterns into a rectangle of the minimum possible area. A number of implementation results are also shown to reveal the practicability of the proposed analog module generator.

This paper describes a modeling of the cryptography based on a concept of Petri nets. Movement of tokens in the net model shows a dynamic behavior of systems. On the other hand, the cryptography is considered as a bit operation, so that we can point out a common property between the net structure and the cryptography, which provides our idea that movement of tokens of the net model corresponds to a bitoperation of the cryptography. Some effective keys in the net model are considered by means of the net elements, which are based on T-invariant and net structures. It is shown that the keys of the net structured cryptography provide reasonable strength comparing with the data encryption standard (DES).

This paper proposes a test case generation method for testing concurrent programs as a black box. Typical applications are system testing for switching systems and inter-operability testing for OSI products. We adopt a two-step approach: first generate the control flow graph which represents global behaviors of a given concurrent program, and then apply conventional test case generation methods for the control flow graph. To generate a control flow graph without state space explosion, the black-box equivalence between system behaviors is introduced. The proposed algorithm generates a minimal control flow graph which consists of representatives of equivalence classes. Two practical techniques for the second step are discussed for a case study using a commercial digital PBX. The results show the feasibility of the proposed method.

Isolation characteristics, which are important factors in designing GaAs ICs, are investigated focusing on leak current between circuit elements on a semi-insulating substrate and on the sidegating effect that results from leak current between MESFETs. We have found that the large leak current comes from the projecting edge, located outside the channel, of the gate electrode and that this leak current is the main cause of the sidegating effect. By taking into account quantitatively evaluated isolation characteristics, we can improve LSI design rules to reproducible and reliable operation.

A Pt-based gate and photochemical dry etching were developed to fabricate N-InAlAs/InGaAs HEMT ICs. The N-InAlAs/Pt contact showed a Schottky barrier at 0.82 eV, about 0.3 eV larger than ΔEc, and nearly ideal I-V characteristics. Its main disadvantage was the excess penetration of Pt into InAlAs. We proposed a thin-Pt/Ti/Au multilayer gate, more thermally stable than the thick-Pt gate, where Ti layer suppresses the above problem with Pt. The multilayer gate also showed a Schottky barrier (φ) of 0.83 eV and an edeality dactor of 1.1. The high φ value makes it possible to fabricate an E-mode N-InAlAs/InGaAs HEMT. We also developed photochemical selective dry etching using CH3Br gas and a low-pressure mercury lamp. The etching selectivity was 25 at an etch rate of 17 nm/min for InGaAs and 0.7 nm/min for InAlAs. The 1.2-µm-gate E-mode HEMT fabricated using the Pt-based gate and photochemical etching had an excellent peak transconductance of 620 mS/mm with a threshold voltage of +0.03 V. The standard deviation of the threshold voltage of E-mode HEMTs on a 2-inch wafer was 20 mV at an average of +0.088 V. These results indicate the effectiveness of the Pt-based gate and photochemical etching for fabricating N-InAlAs/InGaAs HEMT ICs.

Stochastic Petri Nets and Generalized Stochastic Petri Nets as well as other extensions to Stochastic Petri Nets have been widely applied as a model of asynchronous concurrent process, or as an aid to analyze or design concurrent systems. This paper presents an Extended Stochastic Petri Net model for a shift processing system in which three kinds of sink may occur and an arbitrary time distribution is incorporated, provides an analytical method based on a Markov renewal process with some non-regeneration points to clarify the probabilistic behavior of the system, and finally evaluates the performance of the system with numerical values.

The preparation of magnetic semiconductor thick film (MST) by means of spray printing and application to a temperature/gas/essence sensor have been proposed. The MST pattern is composed of ferrite, ruthenium compound, carbon black, binder and solvent. After the mixed mgnetic semiconductor fluid is sprayed on a substrate, the sample is sintered at 750. The MST with thickness of 40 µm is printed on the substrate in various shapes such as a plate, a ring or a rod. The magnetic property of MST depends on temperature, and the electrical property responds to gas and natural/artificial fruit essence. Therefore, the multipore ceramic MST operates as a gas sensor with high sensitivity and high stability.

High frequency and low power 128/129 dual modulus prescaler ICs are developed for mobile communication applications, using 0.5 µm GaAs MESFET technology. Provided with an on-chip voltage regulator, a prescaler IC with an input amplifier operates in a wide frequency range from 200 MHz to 1,500 MHz at input power from -15 dBm to +17 dBm at the temperature of -30 to +120 with supply voltage of 2.7 V, 3.0 V and 5.0 V. At the same time, it demonstrated its low power characteristics consuming 3.68 mA with 3.0 V at +30 in operation, 0.16 mA while powered-off. Another prescaler IC without an input amplifier operates up to 1,650 MHz with Vdd=2.7 V, 3.0 V and 5.0 V at +30, dissipating 2.74 mA/3.0 V.

Recently, Burch et al. proposed symbolic model checking method to verify sequential machines formally. The method, which is based on logic function manipulation using binary decision diagram, can handle large sequential machines that cannot be handled by the conventional techniques. The expressive power of Computational Tree Logic (CTL), which was used by Burch et al., is not very powerful, for example, CTL cannot describe repetition of events. This papers shows an extension of the symbolic model checking algorithm to Branching time regular temporal logic (BRTL), which has been proposed by the authors as an improvement of CTL in terms of expressive power. The implemented verifier based on the proposed algorithm could verify behaviors of a microprocessor composed of approximately 1,600 gates and 68 flipflops.

In this paper, the software structure for telecommunication user support are discussed, and it is proposed to apply knowledge processing technology to the software. Capabilities of telecommunications networks are becoming quite complicated, and the number of service items and parameters which have to be selected and memorized will become too large for telecommunications end users to make full use of the network capabilities. As such, more effort should be focused on assisting telecommunications end users to use the network and providing user friendly human interfaces of the network. However, this kind of software has additional type of requirements other than those for protocol handling software and call control software, and the realization of such support software has not yet been fully studied. To realize such support software, this paper stressed the realization of the user-system interface. Especially identified in this paper are meaning-based interpretation of user inputs to permit the handling of synonyms and multivocations, and a method to access the database in the support system without consideration of its data schema. To satisfy these objectives, this paper has proposed that the application data should be represented in both a character string and a meaning representation, and that the thesauruses should have the attribute-value relation. In line with these studies, an experimental system called CAPRIS (CAlling PRocedure Instruction System) was developed. It is used to assist the calling party in a telecommunications network to find an appropriate contact point depending on the purpose of the communication. Implementation of CAPRIS is completed and it was confirmed that all the functions described in this paper were actually realized. Some functional experiments were performed on CAPRIS, and the system was concluded to realize satisfactory user-friendliness.

The mechanisms for executing concurrent applications proposed so far fall into one of three groups: processes, kernel-level threads, and user-level threads. Each of them is insufficient in terms of either parallelism, the flexibility to combine separately developed programs at run-time, or costs of operations such as creation, switching, and termination. A thread facility in the XERO operating system overcomes this problem and provides a uniform framework for executing concurrent applications. To achieve parallelism of threads, the flexibility to combine separately developed programs at run-time, and fast thread operations, the operating system kernel and a thread management module in a user address space manage threads cooperatively. We implemented the cooperative thread management mechanism and measured its performance to examine the effectiveness of our approach.

This paper describes the integration of a qualitative method and a quantitative method by Bottleneck Diagnosis/Improvement Expert Systems for Synchronized queueing network (BDES-S and BIES-S). On the basis of qualitative reasoning, BDES-S can carry out parameter tuning in order to diagnose and improve bottlenecks of synchronized queueing networks. BDES-S can produce several alternative qualitative improvement plans for one bottleneck server. BIES-S can produce quantitative improvement equations for each qualitative improvement plan. Our method using BDES-S and BIES-S can integrate both quantitative and qualitative methods for parameter tuning on complicated queueing synchronized networks.

In this paper, we propose a method to simulate the curve surface of the initial height in the movement of the electronic wire bonder using the experimental data. For given measured data (xk, yk, zk (k=1, 2, , m)), we propose an algebraic surface of n-th degree as a methematical model of the initial height surface. The AIC method is a method of evaluating the goodness of a given model. The maximum likelihood model is selected by comparing with the AIC value of each model for n=0, 1, 2, 3, , 11. Useing this model, the initial raise position of the electronic wire bonder can be controlled by computer programing and can make the movement of wire bonder full-automatic. As a resurt, the well-arranged wiring and reliable contacting can be obtained.

A passive double star (PDS) optical subscriber system which employs a newly proposed flexible access and frequency division duplex transmission system has been reported. For the flexible access and efficient channel usage in subscriber PDS system, a modified pipe-line polling with a call-by-call basis channel assignment has been proposed. This access system has a wide covering range which exceeds 10km or more. A newly proposed pulsed PSK transmission and a baseband transmission are used for a single wavelength bi-directional transmission for to and from the central office. A pulsed FM single subcarrier transmission system is also proposed for the analog CATV distribution system, which is overlaid with wavelength division multiplexing on the bi-directional transmission system. The equipments for the pulsed PSK and the pulsed FM transmission can be realized with all digital circuits. Moreover, the pulsed signal's modulation nature has eased the requirement for the laser diode characteristics, such as linearity and RIN. These features are effective for the compact and cost effective transmission systems.

The quality of polycrystalline silicon films and electrical characteristics of polycrystalline silicon gate metal-oxide-semiconductor (MOS) capacitors were investigated under various processing conditions, including phosphorus doping. The stresses observed in Si films deposited in the amorphous phase show complex behavior during thermal treatment. The stresses in as-deposited Si films are compressive. They change to tensile with annealing at 800, and to compressive after an additional annealing at 900. The kind of charges trapped in the SiO2 film during the negative constant current stress in Polycrystalline silicon gate MOS capacitors differ with the maximum process temperature. The trapped charges of samples annealed at 800 were negative, while those of samples annealed at 900 were positive.

The characteristics of an optical functional integrated circuit and its applications are discussed. This circuit is based upon a Mach-Zehnder interferometer type waveguide device employing thermo-optic effect. This circuit is compact, cost-effective and practical. One proposed application is an optical loopback circuit to test both OCU loop 1 and DSU loop C. This optical loopback circuit with an attenuator and space switches is formed on a common silicon substrate, and using this circuit both loopback and line tests are independently available at the same access point. The other is an optical selector. This optical selector with WDM-MUX/DMUX and space switches is formed on a common silicon substrate, and using this selector, wavelength selection from medium density WDM (MDWDM) signal can be performed. Each MDWDM signal carries both AM and FM-FDM video signals modulated by Subcarrier Multiplexing (SCM) techniques. This selector can be wired in point-to-multipoint configurations to home video appliances.

The essential functions of the passive double star (PDS) system are clarified by comparing them to the functions of the single star (SS) and the active double star (ADS) system. A layered structure describing the functional characteristics of the PDS system is proposed for flexible transport capability. The functions of the optical network unit (ONU) on the customer premises are systematically partitioned into four layers. The functions of the optical subscriber unit (OSU) in the central office are described using five layers. Call by call activation and deactivation techniques are described on the basis of a layered architecture. The reduction of ONU power consumption by adopting activation and deactivation control is also discussed.

The mode partition noise of 1.3µm distributed feedback laser diodes (DFB LD's), which is induced by the externally reflected light, is studied experimentally and numerically. The mode partition noise is evaluated by the k-value. It is observed that the mode parition noise monotonically increases with the DC bias current when the reflected light affects DFB LD's and the DC bias current is above the threshold current. From the dependence of the k-value on the external power reflection coefficient, it is observed that the k-value dramatically increases when the external power reflection coefficient is above a value which differs from LD to LD. This is closely related to the fact that the tolerance to the externally reflected light depends on the threshold gain difference between the main mode and the dominant side mode.

A novel harmonic retrieval algorithm is proposed in this paper based on Hopfield's neural network. Frequencies can be retrieved with high accuracy and high resolution under low signal to noise ratio (SNR). Amplitudes and phases in harmonic signals can also be estimated roughly by an energy constrained linear projection approach as proposed in the algorithm. Only no less than 2q neurons are necessary in order to detect harmonic siglnals with q different frequencies, where q denotes the number of different frequencies in harmonic signals. Experimental simulations show fast convergence and stable solution in spite of low signal to noise ratio can be obtained using the proposed algorithm.