A vertex-capacitated network is a graph whose edges and vertices have infinite positive capacities and finite positive capacities, respectively. Such a network is a model of a communication system in which capacities of links are much larger than those of stations. This paper considers a problem of realizing a flow-saturation in an undirected vertex-capacitated network by adding the least number of edges. By defining a set of influenced vertex pairs by adding edges, we show the follwing results.(1) It suffices to add the least number of edges to unsaturated vertex pairs for realizing flow-saturation.(2) An associated graph of a flow-unsaturated network defined in this paper gives us a sufficient condition that flow-saturation is realized by adding a single edge.

This paper proposes a new circuit configuration for realizing a type 1 mutator using two current conveyor (CCIIs) and a network with a suitable current transfer function. The advantage of the proposed circuit configuration is that any impedance functions which are proportional to the realizable current transfer function can be simulated.

This paper describes a perspective on Personal Communicatoins Services (PCS) and technological trends. It takes into consideration rules pertaining to the use of PCS for mobile radio communication and countermeasures to cope with the huge increase in PCS subscribers. In this paper, PCS network structures, inter-regional roaming, microcell structure, radio access and channel access methods are also covered as PCS technologies. Furthermore, trends in domestic and international standards are also described. Although these technologies present many difficulties, we believe that they will be overcome and PCS services will be introduced in the near future.

This paper describes voice communication connection controls in digital public land mobile networks (D-PLMNs). Voice communications in the D-PLMNs are carried at about 10 kbit/s over narrow-band TDMA channels with highly efficient cellular voice encoding schemes. Extensive research is being carried on half-rate voice encoding schemes that will effectively double radio resources. We first outline the configuration of voice communication connection between a cellular phone in the D-PLMN and a telephone in a fixed network, and we describe the optimum position for the CODECs that transform cellular voice codes to the conventional voice codes used in the fixed network, and vice versa. Then we propose a CODEC-bypassed communication control scheme that improves the quality of voice communication between cellular phones. And we propose a cellular voice code negotiation scheme in the D-PLMN which supports different cellular voice encoding schemes. We also propose an efficient channel reassignment scheme for effectively assigning TDMA channels to voice calls with two different bitrates (full-rate and half-rate), and we analyze this scheme's traffic capability. Finally, we describe a dual-tone multiple-frequency (DTMF) signal transmission scheme and estimate the number of DTMF signal senders required in the D-PLMN.

This paper describes the higher-order moment analysis of superposed Markov jumping processes. A superposed Markov jumping process is defined as a linear superposition of a finite number of piecewise constant real valued stochastic process whose value changes are associated with state transitions in an underlying descrete state continuous time Markov process. Some phenomena are modeled well by the process such as membrane current fluctuations observed at bio-membranes or load fluctuations in electrical power systems. Theoretical formula of the moment function of any order k is derived and the parameter estimation problem utilizing higher-order moment functions is discussed. A new method of estimating the kinetic parameters of membrane current fluctuations is proposed as a possible application.

Rate based control is a promising way to achieve an efficient packet transmission especially in high speed packet switching networks where round trip delay is much larger than packet transmission time. Although inappropriate tuning for the parameters, increasing and decreasing factors, of the rate control function causes the performance degradation, most of the previous works so far have not studied the effect of the parameters on the performance. In this paper, we investigate the effect of the rate control parameters on the throughput under the condition that the packet loss probability is kept below a specific value, say 10-6. For this purpose, we build a queueing model and carry out a transient analysis to examine the dynamic behavior of the queue length at an intermediate node in a high speed network suffering from large propagation delay. Numerical examples exploit the optimal value of the parameters when one or two source-destination pairs transmit packets. We also discuss the effect of the propagation delay on the performance. Our model can be applicable to investigate the performance of various kinds of rate-based congestion control when the relation between the congestion measure and the rate control mechanism is given explicitly.

In high-speed packet networks, protocol processing overhead time becomes remarkable in determining the system performance. In this paper, we present a new Selective-Repeat ARQ scheme (called Block SR-ARQ sheme), in which a packet is transmitted or retransmitted in the same way as basic SR-ARQ scheme, but a single acknowledgement packet is used to acknowledge a block of packets. The maximum number of packets acknowledged by an acknowledgement packet is defined as block size. We analyze the system throughput and the average packet delay over the system, and the accuracy of approximately analyzed results is validated by simulation. Furthermore, we show that there exists an optimal block size which obtains both the maximum throughput and the minimum average packet delay.

This paper is a study on the behavioral aspects of the input buffer limiting scheme whose basic feature is to award priority to the transit messages over the input messages so that congestion does not develop in the network. The numerical method employed in the analysis is that proposed in Ref.(7). The performance aspects are studied for different buffer capacities, different message handling capacities and different levels of reservation for transit traffic. The numerical method indicates that thrashing occurs at low levels of reservation for the transit messages, irrespective of the buffer size or the processor capacities of the node. This observation is supported by simulation results. With reference to the state-space of the model of our study, the congestion aspects are related to two Liapunov functions. Under the domain of one of the Liapunov functions, the evolution of the perturbed system is towards a congested state whereas, under the domain of the other Liapunov function, the evolution is towards a congestion-free state. Regardless of the configuration, it is found that the fundamental characteristic of the congestion under the input buffer limiting scheme is the characteristic of a fold catastrophe. In the systems with insufficient level of reservation for the transit traffic, the performance degradation appears to be inevitable, irrespective of the capacities of the nodal processor and output channel processor, and the size of the buffer pool. Given such an inevitability, the active life of a node under a typical node configuration is studied by simulation. A suitable performance index is suggested to assess the performance of deadlock-prone nodes.

A non-blocking optomechanical matrix switch has been developed that is assembled using cassettes as units. Switching can be accomplished between two ferrule-terminated-fiber groups by automatic disconnection and reconnection. The fabricated 100100, 3.1-mm-ferrule-pitch, 710W490D500H (mm) switch exhibits a mean insertion loss of 0.78dB in the 1.31-µm wavelength.

The composition of CMOS control circuit and Vertical-Double-Diffused-MOS (VDMOS) power device on a single chip by using Silicon-On-Insulator (SOI) structure is formulated. Because all the MOS transistors in the CMOS control circuit are not isolated by the trenches, the interference phenomenon between SOI and the substrate is studied. Latch-up is detected thus, the construction of a mechanism to prevent latch-up is also studied. To evaluate the SOI CMOS characteristics the effects of voltage fluctuation on the substrate is analized. The latch-up mechanism is also analized by transient device simulation. As a result of this study a guideline for the immunity of latch-up is established, the features of the mechanism are as follows. First, the latch-up trigger is the charging current of the condenser composed of the oxide layer in the SOI structure. Second, latch-up is normally caused by positive feedback between the parasitic PNP-transistor and the parasitic NPN-transistor. However, in this case, electron diffusion toward the P-well is dominant after the parasitic PNP-transistor falls into high level injection. This feature is different from the conventional mechanism. The high level injection is caused by carrier accumulation in the N- region. Considering the above, it is necessary to; (1) reduce the charging current of the condenser, (2) reduce the parasitic resistance in the N- region of SOI, and (3) reduce the carrier accumulation in SOI for immunity from latch-up.

In the present paper we present a mathematical theory for the transient analysis of probabilistic models relevant to communication networks. First we review the z-transform method, the matrix method, and the Laplace transform, as applied to a class of birth-and-death process model that is relevant to characterize network traffic sources. We then show how to develop transient solutions in terms of the eigenvalues and spectral expansions. In the latter half the paper we develop a general theory to solve dynamic behavior of statistical multiplexer for multiple types of traffic sources, which will arise in the B-ISDN environment. We transform the partial differential equation that governs the system into a concise form by using the theory of linear operator. We present a closed form expression (in the Laplace transform domain) for transient solutions of the joint probability distribution of the number of on sources and buffer content for an arbitrary initial condition. Both finite and infinite buffer capacity cases are solved exactly. The essence of this general result is based on the unique determination of unknown boundary conditions of the probability distributions. Other possible applications of this general theory are discussed, and several problems for future investigations are identified.

Modeling and performance analysis have played an important role in the economical design and efficient operation of switching systems, and is currently becoming more important because the switching systems should handle a wide range of traffic characteristics, meeting the grade of service requirements of each traffic type. Without these techniques we could no longer achieve economy and efficiency of the switching systems in complex traffic characteristic environments. From the beginning of research on electronic switching systems offering circuit-switched applications, Stored Program Control (SPC) technology has posed challenges in the area of modeling and performance analysis as well as queueing structure, efficient scheduling, and overload control strategy design. Not only teletraffic engineers and performance analysts, but also queueing theorists have been attracted to this new field, and intensive research activities, both in theory and in practice, have continued over the past two decades, now evolving to even a broader technical field including traditional performance analysis. This article reviews a number of important issues that have been raised and solved, and whose solutions have been reflected in the design of SPC switching systems. It first discusses traffic problems for centralized control systems. It next discusses traffic problems inherent in distributed switching systems.

The embedded Markov processes associated with Markovian queueing systems are closely related, and their relationships are important for establishing an analytical basis for performance evaluation techniques. As a first step, we analyze the embedded processes associated with a general M/M/1 queueing system. Linear transformations between the infinitesimal generators and the transition probability matrices of embedded processes at arrival and departure times are explicitly derived. Based upon these linear transformations, the equilibrium distributions of the system states at arrival and departure times are obtained and expressed in terms of the equilibrium distribution at arbitrary times. The approach presented here uncovers an underlying algebraic structure of M/M/1 queueing systems, and establishes an algebraic methodology for analyzing the equilibrium probabilities of the system states at arrival and departure times for more general Markovian queueing systems.

In this paper, we propose a new network organizing method for packet radio networks, a layered self-organizing method. In the layered self-organizing network, whole service area is divided into multiple sub-areas and one base station is settled in each sub-area. Communication links are settled in shorter time than the conventional self-organizing method. We evaluate the network organizing performance of the method by using simulations.

This paper describes a new soft-error-immune SICOS upward transistor memory cell suitable for ultra-high-speed bipolar RAMs. A cell size of 180 µm2, significantly smaller than the 500 µm2 in the conventional upward transistor cell, is achieved by marging an upward transistor and a Shottky barrier diode. A new very thin polysilicon resistor and 0.5-µm U-groove isolated SICOS technology are used to furher reduce cell size. The memory cell is about 105 times as immune to soft errors as downward transistor cells. A simulation shows that a 256-Kbit RAM with a write cycle time below 3 ns can be made using this memory cell.

The process of room acoustic planning & design can be aided by Binaural Technology. To this end, a three-stage modelling process is proposed that consists of a "sound"-specification phase, a design phase and a work-plan phase. Binaural recording, reproduction and room simulation techniques are used throughout the three phases allowing for subjective/objective specification and surveillance of the design goals. The binaural room simulation techniques involved include physical scale models and computer models of different complexity. Some basics of binaural computer modelling of room acoustics are described and an implementation example is given. Further the general structure of a software system that tries to model important features of the psychophysics of binaural interaction is reported. The modules of the model are: outer-ear simulation, middle-ear simulation, inner-ear simulation, binaural processors, and the final evaluation stage. Using this model various phenomena of sound localization and spatial hearing, such as lateralization, multiple-image phenomena, summing localization, the precedence effect, and auditory spaciousness, can be simulated. Finally, an interesting application of Binaural Technology is presented, namely, a so called Cocktail-Party-Processor. This processor uses the predescribed binaural model to estimate signal parameters of a desired signal which may be distored by any type of interfering signals. In using this strategy, the system is able to even separate the signals of competitive speakers.

The self-checking design using 2-rail logic is one of the most popular design of self-shecking circuits. Even for a self-checking circuit, a test is necessary after VLSI chip or system fabrication, at each time the system is powered, and, under certain circumstances, in the case of maintenance. Therefore, an easy test scheme is desirable for that circuit. A new design method for a 2-rail logic combinational circuit is proposed, where stuck-open and sutck-on faults FETs can be easily detected. In the proposed circuit design, 4 FETs are added to each gate in a conventional 2-rail logic circuit. Two logical gates, DOR and DAND, are also added to the circuit as fault observing gates. Each test consists of a sequence of 3 input vectors, that is, a type of 3-pattern test, ti1ti2ti3. A test can be easily generated and fault observation is easy. Stuck-at fault and stuck-open fault on lines and almost all multiple faults can also be detected by the test. A gate construction method, test generation method, circuit construction method, and several discussions including gate delay increasing are presented.

We discuss fault tolerance of an information disseminating scheme, t-disseminate on a network with N processors, where each processor can send a message to t directions at each round. When N is a power of t+1 and at most tlogt+1N-1 (at most t) processors and/or edges have hailed, logt+1N+(f1)/t rounds (logt+1N+2 rounds) suffice for broadcasting information to all destinations from any source by t-disseminate. For a arbitrary N, logt+1N2f/t1 rounds (logt+1N+2 rounds) suffice for broadcasting information to all destinations from any source by t-disseminate if at most t(logt+1N1)/2 (at most t/2) processors and/or edges have failed.

Fahlman and Lebiere's (FL) learning algorithm begins with a two-layer network and in course of training, can construct various network architectures. We applied FL algorithm to the same three-layer network architecture as a back propagation (BP) network and compared their generalization properties. Simulation results show that FL algorithm yields excellent saturation of hidden units which can not be achieved by BP algorithm and furthermore, has more desirable generalization ability than that of BP algorithm.

This paper describes the superior performances of the NAND EEPROM. Those are 1) a very small cell area: 4.83 µm2 using 0.7 µm design rule, 2) small block size for erasing: 4 Kbyte block erasing for 4 M-bit NAND EEPROM, 3) high speed programming: 180 nsec per byte for 4 M-bit NAND EEPROM, 4) large number of erase/program endurance cycles: more than 105 cycles for 4 M-bit NAND EEPROM. These extended performances coincide with the requirement for the EEPROM to replace magnetic memories such as hard and floppy disks. Especially, it is shown that NAND EEPROM has the capability to enlarge the erase/program endurance up to 3.6108 cycles. This endurance is a result of the erase and program mechanism of the NAND EEPROM cell. Fowler-Nordheim (F-N) tunneling currents flow from the substrate to the floating gate during programming and opposite currents flow during erasing. This bi-polarity F-N tunneling erase/program operation extends the life time of the tunnel oxide which results in an improved endurance.