We propose, for the first time, highly reliable flash-type EEPROM cell fabrication using in-situ multiple rapid thermal processing (RTP) technology. In this study, rapid thermal oxynitridation tunnel oxide (RTONO) film formations followed by in-situ arsenic (As)-doped floating-gate polysilicon growth by rapid thermal chemical vapor deposition (RTCVD) technologies are fully utilized. The results show that after 5104 program/erase (P/E) endurance cycles, the conventional cell shows 65% narrowing of the threshold voltage (Vt) window, whereas the RTONO cell indicates narrowing of less than 20%. A large number of nitrogen atoms (1020 atoms/cm3) are confirmed by secondary ion mass spectrometry (SIMS), pile up at the SiO2/Si interface and distribute into bulk SiO2. It is considered that in the RTONO film stable Si-N bonds are formed which minimize electron trap generation as well as the neutral defect density, resulting in lower Vt shifts in P/E stress. In addition, the RTONO film reduces the number of hydrogen atoms because of final N2O oxynitridation. The SIMS data shows that by the in-situ RTCVD process As atoms (91020 atoms/cm3) are incorporated uniformly into 1000--thick film. Moreover, the RTCVD polysilicon film indicates an extremely flat surface. The time-dependent dielectric breakdown (TDDB) characteristics of interpoly oxide-nitride-oxide (ONO) film exhibited no defect-related breakdown and 5 times longer breakdown time as compared to phosphorus-doped polysilicon film. Therefore, the flash-EEPROM cell fabricated has good charge storing capability.

Characterization of silicon devices incorporating the capacitor which uses ferroelectric thin films as capacitor dielectrics is presented. As cases in point, a DRAM cell capacitor and an analog/digital silicon IC using the thin film of barium strontium titanate (Ba1-xSRxTiO3) are examined. Production and characterization of the ferroelectric thin films are also described, focusing on a Metal Organic Deposition technique and liquid source CVD.

Numerical simulation of multiple semiconductor devices is necessary to analyze dynamic two- and three-dimensional interactions among devices in CMOS inverters, SRAM cells, and other more complicated gates. With the advent of complete 3D process simulation, an alternative to brute-force transient device simulation must be found for large contiguous silicon regions. Our approach differs from brute-force methods in that we focus not on the time-step control but rather on the latency in the system. By latency, we do not mean that activity within parts of the simulation has ceased or has reached a steady state. Rather, we imply that a simpler form of the solution, a macromodel, can be used to decouple the problem into smaller subproblems. This means that while integrating at a particular time-step, the system of device equations needs only to be solved for a subset of nodes, whereas the node device variables approximated by macromodels are treated as fixed boundary conditions. This drastically reduces the size of the system of equations to be solved at each time-step and allows each node to have a different time-step. Because the responses have exponential-like behavior, we aim to approximate carrier and potential values with closed-form exponential macromodels during a time interval. To assure the accuracy of the simulation, we implement several error formula which predict the range of validity of this interval. Moreover, this approach takes advantage of a standard workstation environment (e.g. SparcStation, DECstation, RS6000). This method has been successfully exploited in circuit simulators like SAMSON, which relies on a sophisticated predictor/corrector scheme based on Gear's backward-differentiation formulae (BDF) and depends on partitioning the circuit by inspection. The device simulation problem differs because the partitioning can not be performed by inspection, and the overhead of implementing multi-order BDF would negate the advantage of the decoupling. Instead, we propose the event-driven simulator, AWETOPSY (Asymptotic Waveform Evaluation for Transient Optimized and Partitioned Simulation) that uses automatic partitioning (domain decomposition) and a straightforward second-order integration scheme that we call the power method in conjunction with exponentially-based macromodeling of Asymptotic Waveform Evaluation to exploit the latency. Although Asymptotic Waveform Evaluation (AWE) was originally developed to simplify the solution of linear circuits, we have adapted it to transient device simulation.

Tunneling generation becomes increasingly important in modern devices both as a source of leakage and for special applications. Mostly, the observed phenomena are attributed to band-to-band tunneling, although from early investigations of Esaki diodes it is well known that at lower field strengths trap-assisted tunneling is responsible for non-ideal IV-characteristics. In this paper we apply microscopic models of trap-assisted and band-to-band tunneling, which were derived from first-principle quantum-mechanical calculations, in a general multi-device simulator. Special simplified versions of the models were developed for the purpose of fast numerical computations. We investigate pn-junctions with different doping profiles to reveal the relative contribution of the two tunneling mechanisms. Simulated currents as function of voltage and temperature are presented for each individual process varying the basic physical parameters. It turns out that the slope of reverse IV-characteristics dominated by trap-assisted tunneling is similar to those which are determined by band-to-band tunneling, if the localized state of the recombination center is only weakly coupled to the lattice. In the model such a slope is produced by field-enhancement factors of the Shockley-Read-Hall lifetimes expressing the probability of tunneling into (or out of) excited states of the electron-phonon system. The temperature dependence of these field-enhancement factors compensates to a certain extent the expected strong temperature effect of the Shockley-Read-Hall process. The latter remains larger than the temperature variation of phonon-assisted band-to-band tunneling, but not as much as often stated. Consequently, the slope of the IV-characteristics and their temperature dependence are not the strong criteria to distinguish between trap-assisted and band-to-band tunneling. The origin of tunnel currents in silicon rather depends on the sum of physical conditions: junction gradient, nature and concentration of defects, temperature and voltage range.

New insights pertaining to hot-carrier degradation of CMOS inverters have been obtained using an in-house reliability simulator named HIRES (Hitachi Reliability Simulator). The simulation of three out of four different inverter configurations which utilize series-connected NMOSFET devices between the output node and ground results in higher levels if degradation than that induced by intuition. For two of the configurations--the cascode inverter (where the gate of all NMOSFET's are connected to the input) and the two-input NAND gate--degradation levels are comparable to that of a simple two-transistor CMOS inverter. This high level of degradation is found to be caused by the fact that most of the output voltage is dropped across one of the series-connected NMOSFET transistors rather than being equally divided between the two. From degradation simulation results, a design methodology is developed to optimize the inverter circuits to minimize hot-carrier degradation by balancing the degradation suffered between the two series-connected NMOSFET's. Using this approach, up to a factor of 109 improvement in device lifetime is achieved.

A 10 GHz MMIC predistortion linearizer fabricated on a single chip is demonstrated for the first time. It employs less hybrid circuits compard with conventional devices, and is suitable for miniaturization. The total chip size of the fabricated MMIC is about 3.5 mm3.0 mm. The distortion reduction effect is examined using this linearizer. The improvement in IM3 is more than 15 dB between 10.45 GHz and 10.70 GHz, and more than 8 dB between 10.05 GHz and 10.90 GHz.

Material research on capacitor dielectrics for DRAM applications is reviewed. The state of the art technologies to prepare Si3N4,Ta2O5, and SrTiO3 thin films for capacitors are described. The down-scaling limits for Si3N4 and Ta2O5 capacitors seem to be 3.5 and 1.5 nm SiO2 equivalent thickness, respectively. Combined with a rugged polysilicon electrode surface,Si3N4 and Ta2O5 based-capacitors are available for 256 Mbit and 1 Gbit DRAMs. At the present time, the minimum SiO2 equivalent thickness for high permittivity materials is around 1 nm with the leakage current density of 10-7 A/cm2. Among the great variety of ferroelectrics, two families of materials,i.e., Pb (Zr, Ti) O3 and (Ba, Sr) TiO3 have emerged as the most promising candidates for 1 Gbit DRAMs and beyond. If the chemical vapor deposition technology can be established for these materials, capacitor dielectrics should not be a limiting issue for Gbit DRAMs.

The small-signal negative resistance of QWITT (Quantum Well Transit-Time) diodes is calculated including the effect of field-dependent diffusion coefficient in the frequency range of 10 to 300 GHz. The drift velocity transient effect is also included. The result is compared with those obtained by using constant diffusion coefficients at average electric fields.

We designed and fabricated a prototype 0.4-µm-gate CMOS/SIMOX PLL LSI in order to verify the potential usefulness of ultrathin-film SIMOX technology for creating an extremely low-power LSI containing high-speed circuits operating at frequencies of at least 1 GHz and at low supply voltages. This PLL LSI contains both high-frequency components such a prescaler and low-frequency components such as a shift register, phase frequency comparator, and fixed divider. One application of the LSI could be for synthesizing communication band frequencies in the front-end of a battery-operated wireless handy terminal for personal communications. At a supply voltage of 2 V, this LSI operates at up to 2 GHz while dissipating only 8.4 mW. Even at only 1.2 V, 1 GHz-operation can be obtained with a power consumption of merely 1.4 mW. To explain this low-power feature, we extensively measured the electrical characteristics of individual CMOS/SIMOX basic circuits as well as transistors. Test results showed that the high performance of the LSI is mainly due to the advanced nature of the CMOS/SIMOX devices with low parasitic capacitances around source/drain regions and to the new circuit design techniques used in the dual-modulus prescalar.

This paper reviews the development of low temperature poly Si TFT, scattering light valves addressed by TFTs and a brighter video projection system using them, with the attensin of their optical aspects. The first includes main feature which are laser induced crystallization of PECVD a-Si in almost entirely solid phase by high speed scanning CW Ar laser beam. The second includes photo-polymerization induced phase separation method for the preparation of liquid crystal polymer composite (LCPC) material and scattering light valve with low driving voltage of 6 Vrms. The last gives a brighter video screen image with high contrast ratio and includes higher light efficiency through LCPC light valves and projection lens unit by about four times than that of conventional LC light valves with polarizers.

In this paper the three dimensional (3-D) effect on CMOS latch-up is modeled using a graphical technique based on the fundamental principle of "charge neutrality or its current continuity equivalent" in the base region of parasitic transistors involved in latch-up. The graphical generation of the complete latch-up I-V characteristic requires as an input the SPICE parameters of the relevant bipolar and MOS transistors, the values of shunt resistances and the reverse current-voltage characteristic of the well-substrate junction. The infiuence of the MOS transistor shunting the parasitic bipolar transistors has received special attention. The nonideal scaling of the parasitic resistances has been observed to be the most crucial parameter determining the 3-D nature of the device. The proposed model is validated with test-structures fabricated in 2 µm bulk CMOS technology at and above room temperature. SAFE space map is constructed with width W as a parameter.

As part of Hitachi's development of clean semiconductor processing equipment, the Fluids Modeling Group of the Mechanical Engineering Research Laboratory is developing a computer model, CONTAMINATE, for simulating contamination of wafers in chemical vapor deposition (CVD) systems. CONTAMINATE is based on a 2D implementation of the SIMPLER algorithm for simulating convection/diffusion transport processes. The new model includes modules for simulating fluid flow, heat transfer, chemical reactions, and gas-phase formation and deposition of clusters and particles. CONTAMINATE outputs property fields and estimates of various film quality indices. Using CONTAMINATE we simulated a SiH4: O2: N2 gas mixture at 300 K flowing over a wafer heated to 700 K. System pressures were varied from 1-100 torr and SiH4 pressures from 0.1 to 10 torr. Deposition characteristics are in qualitative agreement with actual systems and are summarized as follows: (1) No particles larger than 0.1µm deposited for any of the conditions tested. (2) Film damage occurred above 10 torr, but no damage occurred below 10 torr. (3) Increasing SiH4 pressure at constant system pressure eliminated particle deposition because particles grew large enought that thermophoresis blocked particle diffusion. (4) Conformal deposition of featured surfaces was achieved only at 1 torr. (5) Film thickness variation over the diameter of the wafer was 15% at 100 torr, 3% at 10 torr, and 1% at 1 torr.