We present several challenging gridding problems for multi-dimensional device and process simulation and discuss how new strategies might contribute to their solution. Formulating grid quality requirements for the standard Scharfetter-Gummel box method discretization in device simulation, we demonstrate how the offsetting techniques compares with quadtree grid generation methods and how they apply to modern device designs. Further we present a grid adaptation approach which respects the grid quality criteria and touch upon the main adaptation difficulties within device simulation. For the 3D moving boundary grids in process simulation we present a new algorithm.

In modems for burst transmission of digital data, rapid carrier and clock synchronization are essential. Typically, frequency correction occurs prior to phase recovery since estimators are sensitive to frequency offsets. In this paper, we derive the bit error rate (BER) performance of a M-ary phase shift keying (MPSK) receiver in a closed form when there is no frequency offset estimator. Then we derive a relationship of the required burst length for certain BER with frequency offset estimator. To obtain the BER=10-4, approximately we need the burst length of 101 at Eb/N0=10 dB and 69 at Eb/N0=15 dB.

The architecture and control procedure for a direct conversion receiver are investigated for a linear modulation scheme. The proposed design techniques maintain receiver linearity despite various types of signal distortion. The techniques include the fast gain control procedure for receiving a control channel for air interface connection, DC offset canceling in both analog and digital stages, and 2nd-order intermodulation distortion canceling in an analog down-conversion stage. Experimental and computer simulation results on PHS (Personal Handy-phone System) parameters, showed that required linear modulation performance was achieved and thus the applicability of the proposed techniques was demonstrated.

This paper reports on the use of microelectronic test structures to characterise a novel fabrication technique for thin-film electronic circuit boards. In this technology circuit tracks are formed on paper-like substrates by depositing films of a metal-loaded ink via a standard lithographic printing process. Sheet resistance and linewidth for both horizontal and vertical lines are electrically evaluated and these compared with optical and surface profiling measurements.

The frequency offset estimation is used to correct any frequency error of the local reference oscillator. In this letter, a frequency offset estimation algorithm utilizing the peak phase error detection and frequency offset smoother is proposed for burst data transmission. The basic idea of frequency offset estimator is to use a curve fitting method. The proposed peak phase error detection avoids a large phase error which yields a bad value for FOE. In order to control the AFC, frequency offset smoother by a simple filter is used. Simulation results show that the proposed algorithm is adequate for frequency offset estimation of burst data transmission.

This paper describes a 2.5-Gb/s optical receiver and transmitter chipset consisting of a preamplifier, a main amplifier, a clock and data recovery (CDR) circuit, and a laser-diode (LD) driver. Low-voltage and adjustment-free circuit techniques are introduced in order to achieve low cost and low power circuits. Circuit adjustments are eliminated by using a multi-stage automatic offset canceling technique in the main amplifier, and by using a PLL structure with a sample-and-hold technique in the CDR circuit. For power reduction, ICs are operated at a power supply voltage of -3 V. Fabricating the ICs by a 0.5-µm Si bipolar process makes it possible to achieve 2.5-Gb/s receiver and transmitter operation with a total power dissipation of 1.04 W. Especially significant is that the receiver ICs need no external devices and adjustments.

DC offset causes performance degradation in signal processing systems especially for high-speed applications. A new offset cancellation method that relaxes the requirement for the offset of the circuit components in the differential analog data path to about 10 times larger is introduced. This method moves the adjusting target from analog-to-digital converter (ADC) to its input buffer and adjusts DC level of ADC input to its center before the final offset cancellation. It eliminates post-production adjustment such as fuse trimming, which increases the cost and TAT in manufacturing and testing. Execution and simulation times are shortened down to 1/9 for less settling time in buffer and with improved logic. An automatic quick offset calibration circuit is implemented in a small silicon space in a high-speed hard disk drive (HDD) channel with 0.25-µm four-layer metal CMOS process. The measured data show this method works effectively in this system.

In this paper, we discuss the initial acquisition of the code division multiplexed DS/SS down-link signals at a user terminal of multiple LEO mobile satellite communication systems. In LEO systems, a receiver generally receives signals from plural satellites for soft hand-off and for satellite diversity as a countermeasure to shadowing. In this situation, the signal from each satellite becomes the interference to the signals from other satellites. In addition to this inter-satellite interference, we have to consider the intra-satellite interference from user channels to a pilot channel because of the loss of orthogonality of channels at initial acquisition stage especially under frequency offsets due to Doppler effect. Thus in this paper, we analytically evaluate the performance of an initial acquisition scheme, taking the intra/inter-satellite interference under Doppler shift into account.

It is important to know phase offsets of a binary code in the field of mobile communications because different phase offsets of the same code are used to distinguish signals received at a mobile station from those of different base stations. When the period of the code is not very long, the relative phase offset between the code and its shifted code can be found by counting the number of bits delayed from the code of the same bit streams. But as the period of the code increases, it becomes difficult to find the phase offset. This paper proposes a new method to calculate the phase offset of a binary code. We define an accumulator function, which is used to calculate the phase offsets between the code and its shifted code. Also the properties of the accumulator function are investigated. This number theoretical approach and its results show that this method is very easy for the phase offset calculation. Its application to the code division multiple access (CDMA) system to define a reference code is given. The simple circuit realization of the accumulator function to calculate the phase offset between the received code and receiver stored replica code is described.

Vehicular speed response phase locked loop (VSR-PLL) is a novel circuit to remove a steady-state frequency offset which arises in the receiver with directive antenna. In this paper, the circuit is applied to Ricean fading environment. For the application of VSR-PLL to Ricean statistics channel, the Doppler shift information of direct wave must be obtained because the self-oscillation frequency of VCO is controlled by using the information. This paper describes an estimation method for the Doppler shift of the direct wave, and shows the several results of the performance analysis for the estimation method and proposed VSR-PLL with the method. As a result, we found that the proposed VSR-PLL could reduce the irreducible bit-error rate for QPSK system from about 10-2 to 10-3 on several conditions.

Although ATM networks support various traffic requirements, but many data applications are unable to precisely specify traffic parameters such as bit rate. These applications generally require a dynamic share of the available bandwidth among all active connections, they are called available-bit-rate (ABR) service. Due to bursty and unpredictable pattern of an ABR data stream, its traffic control is more challenging than other services. In this paper, we present an improved ABR traffic control approach, called Offset Proportional Rate Control Algorithm (OPRCA). The proposed approach achieves high link utilization, low delay and weighted fair sharing among contenting sources according to the predefined OPR. The implementation is much simpler than that of existing schemes. OPRCA combines an end-to-end rate control with link-by-link feedback control, and employs a buffering scheme that avoids Head-of-Line (HOL) blocking. It can dynamically regulate the transmission rate of source traffic and maintain the real fairness among all active connections. Simulation results have shown the effectiveness of OPRCA in several performance aspects.

This paper describes the 10-bit 50 MS/s pipelined CMOS A/D Converter using a "reference feed-forward architecture." In this architecture, reference voltage generated in a reference generator block and residual voltage from a DA/subtractor block are fed to the next stage. The reference generator block and DA/subtractor block are constructed using resistive-load, low-gain differential amplifiers. The high-gain, high-speed amplifiers consuming much power are not used. Therefore, the power consumption of this ADC is reduced. The gain matching of the reference voltage with the internal signal range is achieved through the introduction of the reference generator block having the same characteristics as a DA/subtractor block. Each offset voltage of the differential amplifier in the reference generator block and the DA/subtractor block is canceled by the offset cancellation technique, individually. In addition, the front-end sample/hold circuit is eliminated to reduce power consumption. Because of the introduction of high-speed comparators based on the source follower and latch circuit into the first stage A/D subconverter, analog bandwidth is not degraded. This ADC has been fabricated in double-polysilicon, double-metal, 0.5µm CMOS technology, and it operates at 50 MS/s with a 300-mW (Vdd=3.0 V) power consumption. The differential linearity error of less than +/-1 LSB is obtained.

A wireless communications system with a transmission rate of 10 Mbit/s using Japanese ISM band (2471-2497 MHz) is presented. This system employs a novel spread spectrum multiple access method named "CFO-SS (Carrier Frequency Offset-Spread Spectrum)" method. In the CFO-SS system, a single PN code is commonly assigned to all the multiple carriers, and the frequency offset between the carriers is determined by the information symbol rate, which is small as compared with the spread bandwidth of the signal. Bit error rate performance of the proposed CFO-SS system under multipath environments is investigated by computer simulation, and the performance of the CFO-SS method is confirmed for wireless LAN systems using the 2.4 GHz ISM band.

Recently, the low earth orbit satellite communications has been attracting much attention. These communications have many strong features, however, the communication performances are influenced by carrier frequency offset (CFO) and, particularly, it is hard to acquire the synchronization. A large number of publications have so far been made on the synchronization acquisition of DS/SS systems under CFO and most of them make use of the maximum likelihood decision in finding the maximum values of Fourier transform outputs. However, the implementations of Fourier transforms usually require high cost and large space. In this paper, we propose a new simple acquisition scheme using half-symbol differential decoding technique for DS/SS systems under CFO. This scheme makes use of the addition and subtraction of baseband signals and their delayed versions, (omitting Fourier transforms), together with integrations by recursive integrators, and thus resulting in much simpler implementation. In general, it is shown that the proposed scheme can acquire the code synchronization under carrier frequency offset with much smaller computational complexities and the sacrifice of longer acquisition time.

In this paper, we examine a new initial symbol acquisition method for M-ary spread-spectrum (M-ary/SS) signals that are affected by large carrier frequency offset. By the effect of the carrier frequency offset, preamble signal energy is dispersed to the undersired outputs. The proposed method is based on the collection of such dispersed signal energies by using reference patterns. The reference patterns are constructed by using the characteristic of Hadamard code sequences. The effectiveness of the proposed method is evaluated in terms of mean acquisition time.

This study shows the results of evaluating the flux noises at low frequency when the alternating current(AC) bias direct offset integrated technique(DOIT) with additional positive feedback (APF) is used in a high-Tc dc superconducting quantum interference device (SQUID). The AC-bias DOIT can reduce low-frequency noise without increasing the level of white noise because each operating point in the two voltage-flux characteristics with AC bias can always be optimum on the magnetometer in the high-Tc dc-SQUID. APF can improve the effective flux-to-voltage transfer function so that it can reduce the equivalent flux noise due to the voltage noise of the preamplifier in the magnetometer. The use of APF combined with the AC-bias DOIT reduced the noise of the magnetometer by factors of 1.5 (33µΦ0/Hz vs. 50 µΦ0/Hz) at100 Hz, 3.5 (43 µΦ0/Hz vs. 150 µΦ0/Hz) at 10 Hz, and 5.2 (67 µΦ0/Hz vs. 351 µΦ0/Hz) at 1 Hz as compared with the noise levels that were obtained with the static-current-bias DOIT. The contribution of the factors at 1 Hz is about 2 by APF and 2.6 by AC bias. The performance of improving the flux noise in the AC -bias DOIT with APF is almost equal to that of the flux locked loop (FLL) circuits in which the flux modulation uses a coupling system with a transformer and with the AC bias.

It is well known that offset errors in the multipliers of neural LSIs can have fatal effects on performance. The aim of this study is to understand theoretically how offset errors affect performance of neural LSIs. We have used a single-layer perceptron as an example, and compare our theoretically derived results with computer simulations. We have found that offset errors in the multipliers for the forward process can be canceled out through learning, but those for the updating process cannot be. We have examined the asymptotic behavior of learning for the updating process and derived a mathematical expression for dL, the excess of the averaged loss function L. The derived expression gives us a basis for estimating robustness with respect to the offset errors. Our analysis indicates that dL can be expressed in the form of a quadratic form of offset errors and the inverse of the Hessian matrix of L. We have found that increasing the number of synapses degrades the performacne. We have also learned that enlarging the input signal level and reducing the signal level of the desired response can be effective techniques for reducing the effects of offset errors of the updating process.

In this paper, we propose a novel algorithm for all-digital high speed symbol synchronization to be called the MBECM (Modified-Band Edge Component Maximization). The proposed algorithm has a structure based on the spectral line method. It simplifies and modifies the existing BECM algorithm to compensate for the timing offset caused by different phase characteristics of the BPF (band pass filter) at 1/2T and -1/2T. The algorithm is also independent of the carrier recovery and requires only two samples per symbol for its operation. Until now the timing detector's characteristics of the spectral line method including the M-BECM was not analyzed, particularly effect of the timing offset at convergence point. We analyze the timing detector's characteristics of the M-BECM and derive expressions for the timing detector's mean value (often called the S-curve) as a function of the normalized symbol-clock phase, the rolloff parameterand the bandwidth of the BPF. By using these expressions, the PDbias for eliminating the timing offset at an optimal convergence point are calculated. We also analyze and evaluate performance of the proposed algorithm in various ways such as jitter, timing detector output characteristics, etc. and suggest improvements. The proposed M-BECM is compared to the popular Gardner algorithm for high speed modem applications. The proposed algorithm has simpler structure than the Gardner algorithm and simulation results reveal that the proposed algorithm has better overall performance than the Gardner algorithm in narrow band.

A CMOS programmable gain amplifier (PGA) with a swiched capacitor offset compensation circuit is described. The mean compensation error is 130µV at the input, and the standard deviation of the compensation error is 50µV. This PGA is applicable to a baseband amplifier for digital radio communication terminals.

This paper proposes a novel M-ary FSK demodulation scheme using the Short Time Discrete Fourier Transform (ST-DFT) analysis named Frequency Sequence Estimation (FSE) for low earth orbit (LEO) satellite-based personal multimedia communications. The FSE is a kind of the Viterbi algorithm, searching for the maximum likely frequency path using the instantaneous ST-DFT output as a metric. It is based on the fact that the discrete time-frequency representation of the received signal can be interpreted as a trellis diagram. The proposed method has the excellent transmission performance and spectral efficiency, as well as its own hardware simplicity and frequency offset insensitivity.