Class imbalance is one of the challenges faced in the field of machine learning. It is difficult for traditional classifiers to predict the minority class data. If the imbalanced data is not processed, the effect of the classifier will be greatly reduced. Aiming at the problem that the traditional classifier tends to the majority class data and ignores the minority class data, imbalanced data over-sampling method based on iterative self-organizing data analysis technique algorithm(ISODATA) clustering is proposed. The minority class is divided into different sub-clusters by ISODATA, and each sub-cluster is over-sampled according to the sampling ratio, so that the sampled minority class data also conforms to the imbalance of the original minority class data. The new imbalanced data composed of new minority class data and majority class data is classified by SVM and Random Forest classifier. Experiments on 12 datasets from the KEEL datasets show that the method has better G-means and F-value, improving the classification accuracy.

In OFDM systems, link performance depends heavily on the estimation of symbol-timing and frequency offsets. Performance sensitivity to these estimates is a major drawback of OFDM systems. Timing errors destroy the orthogonality of OFDM signals and lead to inter-symbol interference (ISI) and inter-carrier interference (ICI). The interference due to timing errors can be exploited as a metric for symbol-timing synchronization. In this paper, we propose a novel method to extract interference components using a DFT of the upsampled OFDM signals. Mathematical analysis and formulation are given for the dependence of interference on timing errors. From a numerical analysis, the proposed interference estimation shows robustness against channel dispersion.

We first find simple characterizations of $rac{1}{N} mathbb{Z}$-invariance of arbitrary principal shift-invariant space $V(phi)$. Then we find several equivalent conditions for $V(phi)$ to admit periodic oversampling for a class of continuous frame generators $phi$. In particular, when $phi$ is band-limited and $hat{phi}$ is piecewise continuous, we find very simple and general sufficient conditions for $V(phi)$ to admit periodic oversampling, which involve the extra invariance of $V(phi)$, together with an illustrating example.

We present a multi-channel sampling expansion for signals with selectively tiled band-region. From this we derive an oversampling expansion for any bandpass signal, and show that any finitely many missing samples from two-channel oversampling expansion can always be uniquely recovered. In addition, we find a sufficient condition under which some infinitely many missing samples can be recovered. Numerical stability of the recovery process is also discussed in terms of the oversampling rate and distribution of the missing samples.

We give characterizations of stable scaling functions with compact band regions, which have the oversampling property.

We find necessary and sufficient conditions for the (shifted) oversampling expansions to hold in wavelet subspaces. In particular, we characterize scaling functions with the (shifted) oversampling property. We also obtain L2 and L∞ norm estimates for the truncation and aliasing errors of the oversampling expansion.

Frequency-domain equalization (FDE) based on minimum mean square error (MMSE) is considered as a promising equalization technique for a broadband single-carrier (SC) transmission. When a square-root Nyquist filter is used at a transmitter and receiver to limit the signal bandwidth, the presence of timing offset produces the inter-symbol interference (ISI) and degrades the bit error rate (BER) performance using MMSE-FDE. In this paper, we discuss the mechanism of the BER performance degradation in the presence of timing offset. Then, we propose joint MMSE-FDE & spectrum combining which can make use the excess bandwidth introduced by transmit filter to achieve larger frequency diversity gain while suppressing the negative effect of the timing offset.

This paper proposes a very simple method of eliminating the gain and offset errors caused by mismatches of elements, such as capacitors, for a high-speed CMOS pipelined ADC with a 1.5-bit architecture. The gain and offset errors in a bit-block due to capacitor mismatch are analog-to-digital (A-D) converted without correcting errors, but by exchanging capacitors at every clock. The obtained results are digital codes at the output of the ADC, and they contain positive and negative errors in turn. The two consecutive codes are then added in digital form, thus canceling the errors. This results in the two-fold oversampling operation. As the distortion component arises when the input signal frequency increases, a front-end SHA is used to completely eliminate distortion up to the Nyquist frequency. The behavioral simulation of a 14-bit ADC reveals that this CMOS pipelined ADC with a 1.5-bit bit-block architecture, even without a front-end SHA, has more than 70 dB of spurious-free dynamic range (SFDR) for up to an 8 MHz input signal when each of the upper three bit-blocks has gain and offset errors of +0.8% when the clock frequency is 102.4 MHz. Using an SHA in front further improves the SFDR to 95 dB up to the signal frequency bandwidth of 25.6 MHz.

This paper proposes a jitter tolerant continuous-time sigma-delta A-D converter structure as well as its design method. This method transforms a conventionally designed sigma-delta A-D converter into a jitter tolerant one. Jitter tolerance is provided by the modified feedback signal paths and a consequently inserted digital LPF. This method is applicable independently of a system order and the other specifications.

In an Orthogonal Frequency Division Multiplexing (OFDM) systems, the Peak to Average power Ratio (PAR) is high. The clipping signal scheme is a useful and simple method to reduce the PAR. However, it introduces additional noise that degrades the systems performance. We propose an oversampling scheme to deal with the received signal in order to reduce the clipping noise by using finite impulse response (FIR) filter. Coefficients of the filter are obtained by correlation function of the received signal and the oversampling information at receiver. The performance of the proposed technique is evaluated for frequency selective channel. Results show that the proposed scheme can mitigate the clipping noise significantly for OFDM systems and in order to maintain the system's capacity, the clipping ratio should be larger than 2.5.

This paper presents optimum and sub-optimal designs of noise-shaping FIR filters for single- and multi-bit data converters. In the designs, only three parameters, the number of taps, oversampling ratio (OSR) and l1-norm of the filter coefficients are specified, and the in-band peak of the amplitude response is minimized under the specifications. The minimization problem is formulated with the overload-free condition, which guarantees the rigorous stability, and an overload-free converter generates no distortion in any output signals. In the optimum design, the minimization problem is directly and exactly solved, but the sub-optimal method solves this problem by iteratively utilizing the simplex method. The iterative sub-optimal method without the exact optimality is far faster and more efficient than the optimum method. In design examples, optimum and sub-optimal noise-shaping FIR filters for single- and multi-bit data converters are designed, and their optimal performance is revealed. For single-bit data converters with OSR 64, a noise-shaping FIR filter is designed and then shown to achieve a signal to noise and distortion ratio (SNDR) 107.6 [dB] in the band of interest.

This paper presents an algorithm to analyze the stability and detect an upper-bound of every possible overload of a ΣΔ modulator for a set of input signals that are characterized by specified peak amplitudes and auto-correlations. The approach is to introduce a hyper cube in which all possible state vectors are recursively mapped into a subset of the hyper cube itself for the specified inputs and detect such a hyper cube by iteratively solving linear programming problems. Then the proposed algorithm may not identify every stable ΣΔ modulator but cannot evaluate any unstable ΣΔ modulator as a stable one. In numerical examples, two 1-bit ΣΔ modulators are analyzed, and it is revealed that a band-limitation of inputs to OSR 256 guarantees the rigorous stability even with an extension of input range to at least 240% of conventional range.

An efficient way to optimize the hardware consumption in a low-voltage ΔΣ modulator for D/A converters is described. The modulator employs a ROM selection scheme for multiplications and the new buffer-and-routing ROM structure to minimize the hardware consumption. Furthermore, a guideline of the power-delay-and-area product (PDAP) for compelling issues such as power dissipation, delay time, and chip area consumption in the modern digital-circuit design is proposed. After the validity of the concept has been proved in comparison with that of the conventional guideline of the power-delay product in several behavioral blocks, it was employed in the circuit design. Fabricated in a standard digital 0.35-µm CMOS technology, the modulator achieves a signal-to-noise ratio (SNR) of 96 dB with an oversampling ratio of 256 under the supply of 2.0 V.

This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was implemented with the assumption that there is no frequency deviation that hurts the center of acquired data. The chip has been fabricated using 0.6 µm CMOS technology. The chip has been tested at 1.0 Gb/s NRZ input data with 125 MHz clock and recovers the serial input data into eight 125 Mb/s output stream.

In this paper an analysis on the oversampling data recovery circuit is presented. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance. Theoretical analysis enables us to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the oversampling data recovery circuit for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10-11 BER, 8 times oversampling has about 2 dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits depending on the input data rate and input noise. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5 dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling in white noise dominant input data. The results were applied to the fabricated circuits to validate the analysis.

The fact that bounded interval band orthonormal scaling function shows oversampling property is demonstrated. The truncation error is estimated when scaling function with oversampling property is used to recover signals from their discrete samples.

An oversampling theorem for regular sampling in wavelet subspaces is established. The sufficient-necessary condition for which it holds is found. Meanwhile the truncation error and aliasing error are estimated respectively when the theorem is applied to reconstruct discretely sampled signals. Finally an algorithm is formulated and an example is calculated to show the algorithm.

This paper describes an oversampling analog-to-digital converter (ADC) suitable for PCM codes. Non-linear 5-level quantizer is implemented to noise-shaping modulator. This ADC meets the specifications of ITU-T G.712, in spite of using first order delta-sigma modulator, and realizes low power operation. This chip is fabricated in 0.8 µm double-poly and double-metal CMOS process and occupies a chip area of 15 mm2. Maximum power consumption is 12.8 mW with a single +3 V power supply including DAC and TONE generator.

We present a method of extracting the digital inphase (I) and quadrature (Q) components from oversampled bandpass signals using narrow-band bandpass Hilbert transformers. Down-conversion of the digitized IF signals to baseband and reduction of the quantization noise are accomplished by the multistage decimator with the complex coefficient bandpass digital filters (BPFs), which construct the bandpass Hilbert transformers. Most of the complex coefficient BPFs in the multistage decimator can be replaced with the lowpass filters (LPFs) under some conditions, which reduces computational burden. We evaluate the signal to quantization noise ratio of the I and Q components for the sinusoidal input by computer simulation. Simulation results show that the equivalent amplitude resolution of the I and Q components can be increased by 3 bits in comparison with non-oversampling case.

An integrator using UGB (unity-gain buffer) is proposed. The UGB has gain error. To improve the gain error of UGB in the integrator, a compensation technique of the gain error of UGB is proposed. Next, second-order ΣΔ A/D converter using UGB integrator with gain-error compensator is proposed. In the proposed circuit, the influence of input-output characteristic is simulated. In the simulation results, the improvement is confirmed. In addition, performance limiting factors due to non ideal effects, e.g., parasitic capacitance and offset voltage, are considered. Validity of the proposed compensation technique for each factor is confirmed in the simulation results.