This paper proposes the use of on-chip monitor circuits to detect process shift and process spread for post-silicon diagnosis and model-hardware correlation. The amounts of shift and spread allow test engineers to decide the correct test strategy. Monitor structures suitable for detection of process shift and process spread are discussed. Test chips targeting a nominal process corner as well as 4 other corners of “slow-slow”, “fast-fast”, “slow-fast” and “fast-slow” are fabricated in a 65nm process. The monitor structures correctly detects the location of each chip in the process space. The outputs of the monitor structures are further analyzed and decomposed into the process variations in threshold voltage and gate length for model-hardware correlation. Path delay predictions match closely with the silicon values using the extracted parameter shifts. On-chip monitors capable of detecting process shift and process spread are helpful for performance prediction of digital and analog circuits, adaptive delay testing and post-silicon statistical analysis.

The multivariate public key cryptosystem (MPKC), which is based on the problem of solving a set of multivariate systems of quadratic equations over a finite field, is expected to be secure against quantum attacks. Although there are several existing schemes in MPKC that survived known attacks and are much faster than RSA and ECC, there have been few discussions on security against physical attacks, aside from the work of Okeya et al. (2005) on side-channel attacks against Sflash. In this study, we describe general fault attacks on MPKCs including Big Field type (e.g. Matsumoto-Imai, HFE and Sflash) and Stepwise Triangular System (STS) type (e.g. UOV, Rainbow and TTM/TTS). For both types, recovering (parts of) the secret keys S,T with our fault attacks becomes more efficient than doing without them. Especially, on the Big Field type, only single fault is sufficient to recover the secret keys.

Recently, some cryptographic primitives have been described that are based on the supposed hardness of finding an isogeny between two supersingular elliptic curves. As a part of such a primitive, Charles et al. proposed an algorithm for computing sequences of 2-isogenies. However, their method involves several redundant computations. We construct simple algorithms without such redundancy, based on very compact descriptions of the 2-isogenies. For that, we use some observations on 2-torsion points.

In this paper, we have addressed the problem of ordering transactions in network-on-chips (NoCs) for post-silicon validation. The main idea is to extract the order of the transactions from the local partial orders in each NoC tile based on a set of “happened-before” rules, assuming transactions do not have a timestamp. The assumption is based on the fact that implementation and usage of a global time as timestamp in such systems may not be practical or efficient. When a new transaction is received in a tile, we send special messages to the neighboring tiles to inform them regarding the new transaction. The process of sending those special messages continues recursively in all the tiles that receive them until another such special message is detected. This way, we relate local orders of different tiles with each other. We show that our method can reconstruct the correct transaction orders when communication delays are deterministic. We have shown the effectiveness of our method by correctly ordering the transaction in NoCs with mesh and torus topologies with different sizes from 5*5 to 9*9. Also, we have implemented the proposed method in hardware to show its feasibility.

Post-silicon tuning is attracting a lot of attention for coping with increasing process variation. However, its tuning cost via testing is still a crucial problem. In this paper, we propose tuning-friendly body bias clustering with multiple bias voltages. The proposed method provides a small set of compensation levels so that the speed and leakage current vary monotonically according to the level. Thanks to this monotonic leveling and limitation of the number of levels, the test-cost of post-silicon tuning is significantly reduced. During the body bias clustering, the proposed method explicitly estimates and minimizes the average leakage after the post-silicon tuning. Experimental results demonstrate that the proposed method reduces the average leakage by 25.3 to 51.9% compared to non clustering case. In a test case of four clusters, the number of necessary tests is reduced by 83% compared to the conventional exhaustive test approach. We reveal that two bias voltages are sufficient when only a small number of compensation levels are allowed for test-cost reduction. We also give an implication on how to synthesize a circuit to which post-silicon tuning will be applied.

We introduce an efficient fully simulatable construction of oblivious transfer based on the McEliece assumptions in the common reference string model. This is the first efficient fully simulatable oblivious protocol based on coding assumptions. Moreover, being based on the McEliece assumptions, the proposed protocol is a good candidate for the post-quantum scenario.

In disaster sites of 2011 Tohoku Earthquake, digital communication was virtually unavailable due to the serious damage to the existing Internet and ICT resources. Thus there were urgent demands for recovering the Internet connectivity and first aid communication tools. This paper describes the design and deployment of networking systems that provide Internet connectivity using 3G mobile links or VSAT satellite links. In this paper we examine two approaches for post-disaster networking: quickly deployable package and on-demand networking. Based on a comparison of their characteristics and deployment experiences, this paper tries to extract lessons that contribute to improving the preparedness to another disaster. This paper also shares our significant operational experience acquired through supporting a maximum of 54 sites in Tohoku area including evacuation shelters, temporary hospitals and local government offices.

We implement one-out-of-two bit oblivious transfer (OT) based on the assumptions used in the McEliece cryptosystem: the hardness of decoding random binary linear codes, and the difficulty of distinguishing a permuted generating matrix of Goppa codes from a random matrix. To our knowledge this is the first OT reduction to these problems only. We present two different constructions for oblivious transfer, one based on cut-and-chose arguments and another one which is based on a novel generalization of Bennett-Rudich commitments which may be of independent interest. Finally, we also present a variant of our protocol which is based on the Niederreiter cryptosystem.

In this paper, we present a maximum a posteriori probability (MAP) approach to the problem of blind estimation of single-input, multiple-output (SIMO), finite impulse response (FIR) channels. A number of methods have been developed to date for this blind estimation problem. Some of those utilize prior knowledge on input signal statistics. However, there are very few that utilize channel statistics too. In this paper, the unknown channel to be estimated is assumed as the frequency-selective Rayleigh fading channel, and we incorporate the channel prior distributions (and hyperprior distributions) into our model in two different ways. Then for each case an iterative MAP estimator is derived approximately. Performance comparisons over existing methods are conducted via numerical simulation on randomly generated channel coefficients according to the Rayleigh fading channel model. It is shown that improved estimation performance can be achieved through the MAP approaches, especially for such channel realizations that have resulted in large estimation error with existing methods.

We propose a high-speed and low-complexity architecture for the very large-scale integration (VLSI) implementation of the maximum a posteriori probability (MAP) algorithm suited to the double binary turbo decoder. For this purpose, equation manipulations on the conventional Linear-Log-MAP algorithm and architectural optimization are proposed. It is shown by synthesized simulations that the proposed architecture improves speed, area and power compared with the state-of-the-art Linear-Log-MAP architecture. It is also observed that the proposed architecture shows good overall performance in terms of error correction capability as well as decoder hardware's speed, complexity and throughput.

A reliable antifuse scheme has been very hard to build, which has precluded its implementation in DRAM products. We devised a very reliable multi-cell structure to cope with the large process variation in the DRAM-cell-capacitor type antifuse system. The programming current did not rise above 564 µA even in the nine-cell case. The cumulative distribution of the successful rupture in the multi-cell structure could be curtailed dramatically to less than 15% of the single-cell's case and the recovery problem of programmed cells after the thermal stress (300) had disappeared. In addition, we also presented a Post-Package Repair (PPR) scheme that could be directly coupled to the external high-voltage power rail via an additional pin with small protection circuits, saving the chip area otherwise consumed by the internal pump circuitry. A 1 Gbit DDR SDRAM was fabricated using Samsung's advanced 50 nm DRAM technology, successfully proving the feasibility of the proposed antifuse system implemented in it.

In this paper a third-order inter-modulation cancellation technique using Pre-Post-Distortion is proposed to design a wideband high linear low-power LNA in deep submicron. The IM3 cancellation is achieved by post-distorting signal inversely after it is pre- distorted in the input trans-conductance stage during amplification process. The operating frequency range of the LNA is 800 MHz–5 GHz. The proposed technique increases input-referred third-order intercept point (IIP3) and input 1 dB Compression point (P-1 dB) to 12–25 dBm and -1.18 dBm, respectively. Post layout simulation results show a noise figure (NF) of 4.1–4.5 dB, gain of 13.7–13.9 dB and S11 lower than -13 dB while consumes 8 mA from 1.2 V supply. The LNA is designed in a 65 nm standard CMOS technology. The layout schematic shows that the LNA occupies 0.150.11 mm2 of silicon area.

Post-silicon debugging is getting even more critical to shorten the time-to-market than ever, as many more bugs escape pre-silicon verification according to the increasing design scale and complexity. Post-silicon debugging is generally harder than pre-silicon debugging due to the limited observability and controllability of internal signal values. Conventionally, simulation of corresponding low-level designs such as RTL or gate-level has been used to get observability and controllability, which is inefficient for contemporary large designs. In this paper, we introduce a post-silicon debugging approach using simulation of high-level designs, instead of low-level designs. To realize such a debugging approach, we propose an I/O sequence mapping method that converts I/O sequences of chip executions to those of the corresponding high-level design. First, we provide a formal definition of I/O sequence mapping and relevant notions. Then, based on the definition, we propose an I/O sequence mapping method by executing FSMs representing the interface specifications of the target design. Also, we propose an implementation of the proposed method to get further efficiency. We demonstrate that the proposed method can be effectively applied to several practical design examples with various interfaces.

For an indoor area where a target node is tracked with anchor nodes, we can calculate the priori probability density functions (pdfs) on the distances between the target and anchor nodes by using its shape, three-dimensional sizes and anchor nodes locations. We call it “the area layout information (ALI)” and apply it for two indoor target tracking methods with received signal strength indication (RSSI) assuming a square location estimation area. First, we introduce the ALI to a target tracking method which tracks a target using the weighted sum of its past-to-present locations by a simple infinite impulse response (IIR) low pass filter. Second, we show that the ALI is applicable to a target tracking method with a particle filter where the motion of the target is nonlinearly modelled. The performances of the two tracking methods are evaluated by not only computer simulations but also experiments. The results demonstrate that the use of ALI can successfully improve the location estimation performance of both target tracking methods, without huge increase of computational complexity.

This paper describes a new technique for the design of 3-terminal regulators in which the output voltage level can be adjusted without additional terminals or extra off-chip components. This circuit restricts the increase in the number of terminal pins by using a pin as both a voltage supply output and a voltage setup input. The voltage setup information is introduced using a serial control signal from outside the chip. Using the intermediate voltage level between the supply voltage and the regulator output, the adjustment data in the internal nonvolatile memory are safely updated without noise disturbance. To input the setup information into the chip in a stable manner, we developed a new 1-wire serial interface which combines key pattern matching and burst signal detection. To ensure high reliability, we suggested a quantitative method for evaluating the influence of noise in our new interface using a simple model with superimposed random noise. Circuits additional to those for a conventional 3-terminal regulator, include a 1-wire serial communication circuit, a low-capacity non-volatile memory, and a digital to analog (D/A) converter. A test chip was developed using 0.35 µm standard CMOS process, and there was almost no overhead to the conventional 3-terminal regulator in both chip area and power dissipation. In an on-board test with the test chip, we confirmed successful output voltage adjustment from 1.0 V to 2.7 V with approximately 6.5 mV precision.

This paper presents the loss factors in the post-wall waveguide-fed parallel-plate slot array antenna in the millimeter-wave band. At first, transmission loss is evaluated per unit length by measuring the losses of post-wall waveguides on various substrates with different thicknesses in different bands. Measured results of the frequency dependence agree with theoretical predictions using the effective conductivity and the complex permittivity obtained by the whispering gallery mode resonator method. Then the authors evaluate the antennas with various sizes at 76.5 GHz. The antenna efficiency is evaluated by taking into account the loss factors related to: the transmission loss both in the feed and the parallel plate waveguides, the aperture efficiency and the insertion loss and the reflection of the transition. Also, the loss due to the locally-perturbed currents by the slot radiation is evaluated. The sum of the losses in the prediction quantitatively agrees with the measurement.

Post-wall waveguide with a linear array of reflection-canceling slot pairs and center-feed is designed to cancel the frequency dependent tilting of the main beam and enhance the bandwidth of the antenna boresight gain. The array is fed at the center of the waveguide from the backside; the length of the radiating waveguide is halved and the long line effect in traveling wave operation is suppressed. Authors establish the array design procedure in separate steps to reduce the computational load in the iterative optimization by using Ansoft HFSS simulator. A center-feed linear array as well as an end-feed equivalent with uniform excitation is designed for 25.6 GHz operation and measured. The measured performances confirm the design and the advantage of the centre-feed; a frequency independent boresight beam is observed and the frequency bandwidth for 3 dB gain reduction is enhanced by 1.5 times compared to the end-feed array.

Kernel logistic regression (KLR) is a powerful and flexible classification algorithm, which possesses an ability to provide the confidence of class prediction. However, its training--typically carried out by (quasi-)Newton methods--is rather time-consuming. In this paper, we propose an alternative probabilistic classification algorithm called Least-Squares Probabilistic Classifier (LSPC). KLR models the class-posterior probability by the log-linear combination of kernel functions and its parameters are learned by (regularized) maximum likelihood. In contrast, LSPC employs the linear combination of kernel functions and its parameters are learned by regularized least-squares fitting of the true class-posterior probability. Thanks to this linear regularized least-squares formulation, the solution of LSPC can be computed analytically just by solving a regularized system of linear equations in a class-wise manner. Thus LSPC is computationally very efficient and numerically stable. Through experiments, we show that the computation time of LSPC is faster than that of KLR by two orders of magnitude, with comparable classification accuracy.

In this paper, the robustness of the posterior-based confidence measures is improved by utilizing entropy information, which is calculated for speech-unit-level posteriors using only the best recognition result, without requiring a larger computational load than conventional methods. Using different normalization methods, two posterior-based entropy confidence measures are proposed. Practical details are discussed for two typical levels of hidden Markov model (HMM)-based posterior confidence measures, and both levels are compared in terms of their performances. Experiments show that the entropy information results in significant improvements in the posterior-based confidence measures. The absolute improvements of the out-of-vocabulary (OOV) rejection rate are more than 20% for both the phoneme-level confidence measures and the state-level confidence measures for our embedded test sets, without a significant decline of the in-vocabulary accuracy.

A post-wall center-feed waveguide consisting of T-junctions is proposed for reducing the slot-free area of a parallel plate slot array antenna. The width of the slot-free area is reduced from 2.6 λ0 to 2.1 λ0. A sidelobe level in the E-plane is expected to be suppressed lower than that of the conventional center-feed antenna using cross-junctions. The method of moments with solid-wall replacement designs initially the T-junctions and HFSS including the post surfaces modifies only the reflection cancelling post. We have designed and fabricated a 61.25 GHz model antenna with uniform aperture illumination. The sidelobe level in the E-plane is suppressed to -9.5 dB while that of a conventional cross-junction type is -7.8 dB. Also, we suppress it to -13.8 dB by introducing a -8.3 dB amplitude tapered distribution in the array of the radiation slot pairs.