With the advent of gated quantum computers and the regular structures for qubit layout, methods for placement, routing, noise estimation, and logic to hardware mapping become imminently required. In this paper, we propose a method for quantum circuit layout that is intended to solve such problems when mapping a quantum circuit to a gated quantum computer. The proposed methodology starts by building a Circuit Interaction Graph (CIG) that represents the ideal hardware layout minimizing the distance and path length between the individual qubits. The CIG is also used to introduce a qubit noise model. Once constructed, the CIG is iteratively reduced to a given architecture (qubit coupling model) specifying the neighborhood, qubits, priority, and qubits noise. The introduced constraints allow us to additionally reduce the graph according to preferred weights of desired properties. We propose two different methods of reducing the CIG: iterative reduction or the iterative isomorphism search algorithm. The proposed method is verified and tested on a set of standard benchmarks with results showing improvement on certain functions while in average improving the cost of the implementation over the current state of the art methods.

Stabilizer-based quantum secret sharing has two methods to reconstruct a quantum secret: The erasure correcting procedure and the unitary procedure. It is known that the unitary procedure has a smaller circuit width. On the other hand, it is unknown which method has smaller depth and fewer circuit gates. In this letter, it is shown that the unitary procedure has smaller depth and fewer circuit gates than the erasure correcting procedure which follows a standard framework performing measurements and unitary operators according to the measurements outcomes, when the circuits are designed for quantum secret sharing using the [[5, 1, 3]] binary stabilizer code. The evaluation can be reversed if one discovers a better circuit for the erasure correcting procedure which does not follow the standard framework.

Most quantum circuits require SWAP gate insertion to run on quantum hardware with limited qubit connectivity. A promising SWAP gate insertion method for blocks of commuting two-qubit gates is a predetermined swap strategy which applies layers of SWAP gates simultaneously executable on the coupling map. A good initial mapping for the swap strategy reduces the number of required swap gates. However, even when a circuit consists of commuting gates, e.g., as in the Quantum Approximate Optimization Algorithm (QAOA) or trotterized simulations of Ising Hamiltonians, finding a good initial mapping is a hard problem. We present a SAT-based approach to find good initial mappings for circuits with commuting gates transpiled to the hardware with swap strategies. Our method achieves a 65% reduction in gate count for random three-regular graphs with 500 nodes. In addition, we present a heuristic approach that combines the SAT formulation with a clustering algorithm to reduce large problems to a manageable size. This approach reduces the number of swap layers by 25% compared to both a trivial and random initial mapping for a random three-regular graph with 1000 nodes. Good initial mappings will therefore enable the study of quantum algorithms, such as QAOA and Ising Hamiltonian simulation applied to sparse problems, on noisy quantum hardware with several hundreds of qubits.

The Variational Quantum Eigensolver (VQE) algorithm is gaining interest for its potential use in near-term quantum devices. In the VQE algorithm, parameterized quantum circuits (PQCs) are employed to prepare quantum states, which are then utilized to compute the expectation value of a given Hamiltonian. Designing efficient PQCs is crucial for improving convergence speed. In this study, we introduce problem-specific PQCs tailored for optimization problems by dynamically generating PQCs that incorporate problem constraints. This approach reduces a search space by focusing on unitary transformations that benefit the VQE algorithm, and accelerate convergence. Our experimental results demonstrate that the convergence speed of our proposed PQCs outperforms state-of-the-art PQCs, highlighting the potential of problem-specific PQCs in optimization problems.

Mixed-Polarity Multiple-Control Toffoli (MPMCT) gates are generally used to implement large control logic functions for quantum computation. A logic circuit consisting of MPMCT gates needs to be mapped to a quantum computing device that invariably has a physical limitation, which means we need to (1) decompose the MPMCT gates into one- or two-qubit gates, and then (2) insert SWAP gates so that all the gates can be performed on Nearest Neighbor Architectures (NNAs). Up to date, the above two processes have only been studied independently. In this work, we investigate that the total number of gates in a circuit can be decreased if the above two processes are considered simultaneously as a single step. We developed a method that inserts SWAP gates while decomposing MPMCT gates unlike most of the existing methods. Also, we consider the effect on the latter part of a circuit carefully by considering the qubit placement when decomposing an MPMCT gate. Experimental results demonstrate the effectiveness of our method.

Recently, we demonstrated a rapid-single-flux-quantum NOT gate comprising a toggle storage loop. In this paper, we present our design and operation of a NOR gate that is a straightforward extension of the NOT gate by attaching a confluence buffer. Parameter margins wider than ±28% were confirmed in simulation. Functional tests using Nb integrated circuits demonstrated correct NOR operation with a bias margin of ±21%.

A rapid single-flux-quantum (RSFQ) truncated multiplier based on bit-level processing is proposed. In the multiplier, two operands are transformed to two serialized patterns of bits (pulses), and the multiplication is carried out by processing those bits. The result is obtained by counting bits. By calculating in bit-level, the proposed multiplier can be implemented in small area. The gate level design of the multiplier is shown. The layout of the 4-bit multiplier was also designed.

The recent rapid increase in the scale of superconducting quantum computing systems greatly increases the demand for qubit control by digital circuits operating at qubit temperatures. In this paper, superconducting digital circuits, such as single-flux quantum and adiabatic quantum flux parametron circuits are described, that are promising candidates for this purpose. After estimating their energy consumption and speed, a conceptual overview of the superconducting electronics for controlling a multiple-qubit system is provided, as well as some of its component circuits.

Superconducting single-flux-quantum (SFQ) device is an emerging device which can realize digital circuits with high switching speed and low power consumption. In SFQ digital circuits, voltage pulses are used for carrier of information, and the representation of logic values is different from that of CMOS circuits. Design methods exclusive to SFQ circuits have been developed. In this paper, we present timing analysis and functional verification methods for SFQ circuits based on new timing model which we call delay-based time frame model. Assuming that possible pulse arrival is periodic, the model defines comprehensive time frames and representation of logic values. In static timing analysis, expected pulse arrival time is checked based on the model, and the order among pulse arrival times is calculated for each logic gate. In functional verification, the circuit behavior is abstracted in a form similar to a synchronous sequential circuit using the order of pulse arrival times, and then the behavior is verified using formal verification tools. Using our proposed methods, we can verify the functional behavior of SFQ circuits with complex clocking scheme, which appear often in practical design but cannot be dealt with in existing verification method. Experimental results show that our method can be applied to practical designs.

We report the energy-efficient optical input interface using NbN superconducting nanowire-based optical-to-electrical (SN-OE) converters for a single-flux-quantum (SFQ) data processing system. The SN-OE converters with small active areas ranging from 1$, imes,$1 to 10$, imes,$10,$mu$m$^2$ were fabricated to improve the recovery time by reducing the kinetic inductance of the nanowire. The SN-OE with the smallest area of 1$, imes,$1 $mu$m$^2$ showed the recovery time of around 0.3 ns, while its detection efficiency for a single photon was reduced below 0.1% due to insufficient coupling efficiency with a single-mode optical fiber. However, the optical power dependence of the error rate of this device showed that the required optical power to achieve the error rate below $10^{-12}$ at 10 GHz operation is as large as 70 $mu$W, which is still one order of magnitude lower than semiconductor photo diodes. We also demonstrated the operation of the SN-OE converters combined with the SFQ readout circuit and confirmed the operating speed up to 77~MHz.

A readout technique using single-flux-quantum (SFQ) circuits enables superconducting single photon detectors (SSPDs) to operate at further high-speed, where a mutually-coupled dc-to-SFQ (MC-dc/SFQ) converter is used as an interface between SSPDs and SFQ circuits. In this work, we investigated pulse response of the MC-dc/SFQ converter. We employed on-chip pulse generators to evaluate pulse response of the MC-dc/SFQ converter for various pulses. The MC-dc/SFQ converter correctly operated for the pulse current with the amplitude of 52,$mu$A and the width of 179,ps. In addition, we examined influence of the pulse amplitude and width to operation of the MC-dc/SFQ converter by numerical simulation. The simulation results indicated that the MC-dc/SFQ converter had wide operation margins for pulse current with amplitudes of 30--60,$mu$A irrespective of the pulse widths.

We describe a large-scale integrated circuit (LSI) design of rapid single-flux-quantum (RSFQ) circuits and demonstrate several reconfigurable data-path (RDP) processor prototypes based on the ISTEC Advanced Process (ADP2). The ADP2 LSIs are made up of nine Nb layers and Nb/AlOx/Nb Josephson junctions with a critical current density of 10kA/cm2, allowing higher operating frequencies and integration. To realize truly large-scale RSFQ circuits, careful design is necessary, with several compromises in the device structure, logic gates, and interconnects, balancing the competing demands of integration density, design flexibility, and fabrication yield. We summarize numerical and experimental results related to the development of a cell-based design in the ADP2, which features a unit cell size reduced to 30-µm square and up to four strip line tracks in the unit cell underneath the logic gates. The ADP LSIs can achieve ∼10 times the device density and double the operating frequency with the same power consumption per junction as conventional LSIs fabricated using the Nb four-layer process. We report the design and test results of RDP processor prototypes using the ADP2 cell library. The RDP processors are composed of many arrays of floating-point units (FPUs) and switch networks, and serve as accelerators in a high-performance computing system. The prototypes are composed of two-dimensional arrays of several arithmetic logic units instead of FPUs. The experimental results include a successful demonstration of full operation and reconfiguration in a 2×2 RDP prototype made up of 11.5k junctions at 45GHz after precise timing design. Partial operation of a 4×4 RDP prototype made up of 28.5k-junctions is also demonstrated, indicating the scalability of our timing design.

Superconducting Single-Flux-Quantum (SFQ) devices have been paid much attention as alternative devices for digital circuits, because of their high switching speed and low power consumption. For large-scale circuit design, the role of computer-aided design environment is significant. As the characteristics of the SFQ devices are different from conventional devices, a new design environment is required. In this paper, we propose a new timing-aware circuit description method which can be used for SFQ circuit design. Based on the description and the dedicated algorithms we have been developing for SFQ logic circuit design, we propose an integrated design flow for SFQ logic circuits. We have designed a circuit using our developed design tools along with the design flow and demonstrated the correct operation.

In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.

A physical random number generator, which generates truly random number trains by using the randomness of physical phenomena, is widely used in the field of cryptographic applications. We have developed an ultra high-speed superconductive physical random number generator that can generate random numbers at a frequency of more than 10 GHz by utilizing the high-speed operation and high-sensitivity of superconductive integrated circuits. In this study, we have statistically evaluated the quality of the random number trains generated by the superconductive physical random number generator. The performances of the statistical tests were based on a test method provided by National Institute of Standards and Technology (NIST). These statistical tests comprised several fundamental tests that were performed to evaluate the random number trains for their utilization in practical cryptographic applications. We have generated 230 random number trains consisting of 20,000-bits by using the superconductive physical random number generator fabricated by the SRL 2.5 kA/cm2 Nb standard process. The generated random number trains passed all the fundamental statistical tests. This result indicates that the superconductive random number generator can be sufficiently utilized in practical applications.

We demonstrated an automated passive-transmission-line routing tool for single-flux-quantum (SFQ) circuits. The tool is based on the A* algorithm, which is widely used in CMOS LSI design, and tuned for microstrip/strip lines formed in the SRL 4-Nb layer structure. In large-scale SFQ circuits with 10000-20000 Josephson junctions, such as microprocessors, 80-90% of the wires can be automatically routed in about ten minutes. We verified correct operation above 40 GHz for an automatically routed 44 switch circuit from on-chip high-speed tests. The resulting circuit size and operating frequency were comparable to those of a manually designed result. We believe that the tool is useful for large-scale SFQ circuit design using conventional fabrication processes.

A single flux quantum (SFQ) logic cell library has been developed for the 10 kA/cm2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5 kA/cm2 to 10 kA/cm2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400 GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100 GHz.

Quantum computations have so far proved to be more powerful than classical computations, but quantum computers still have not been put into practical use due to several technical issues. One of the most serious problems for realizing quantum computers is decoherence that occurs inevitably since our apparatus are surrounded with environment and open systems. In this paper, we give some surveys on a variety of effects of decoherence in quantum algorithms such as Grover's database search and quantum walks, and we show how quantum algorithms work under decoherence, how sensitive they are against decoherence, and how to implement a robust quantum circuit.

Quantum circuits for elementary arithmetic operations are important not only for implementing Shor's factoring algorithm on a quantum computer but also for understanding the computational power of small quantum circuits, such as linear-size or logarithmic-depth quantum circuits. This paper surveys some recent approaches to constructing efficient quantum circuits for elementary arithmetic operations and their applications to Shor's factoring algorithm. It covers addition, comparison, and the quantum Fourier transform used for addition.

Recently much attention has been paid to quantum circuit design to prepare for the future "quantum computation era." Like the conventional logic synthesis, it should be important to verify and analyze the functionalities of generated quantum circuits. For that purpose, we propose an efficient verification method for quantum circuits under a practical restriction. Thanks to the restriction, we can introduce an efficient verification scheme based on decision diagrams called Decision Diagrams for Matrix Functions (DDMFs). Then, we show analytically the advantages of our approach based on DDMFs over the previous verification techniques. In order to introduce DDMFs, we also introduce new concepts, quantum functions and matrix functions, which may also be interesting and useful on their own for designing quantum circuits.