A compact and stable optical sampling measurement system with a temporal resolution of 2 ps has been developed. External-cavity mode-locked laser-diode (EC-MLLD) modules, which directly generate coherent 2-ps optical pulses, were used as the optical sampling pulse sources. Real-time measurement of the recovery dynamics in semiconductor saturable absorber devices has been achieved by optical sampling combined with the pump-probe method. An EC-MLLD module was also utilized for simple sub-harmonic all-optical clock recovery based on the synchronization of the mode-locking operation by optical-pulse injection. Optical sampling measurement of 160-Gbit/s return-to-zero signals incorporating all-optical clock recovery has been demonstrated.

An adaptive 4-state phase-frequency detector (PFD) for clock and data recovery (CDR) PLL of non return to zero (NRZ) data is presented. The PLL achieves false-lock free operation with rapid frequency-capture and wide bit-rate-capture range. The variable bit rate operation is achieved by adaptive delay control of data delay. Circuitry and overall architecture are described in detail. A z-Domain analysis is also presented.

Because it has desirable features such as no cascading rollback, fast output commit and asynchronous logging, causal message logging needs a consistent recovery algorithm to tolerate concurrent failures. For this purpose, Elnozahy proposed a centralized recovery algorithm to have two practical benefits, i.e. reducing the number of stable storage accesses and imposing no restriction on the execution of live processes during recovery. However, the algorithm with independent checkpointing may force the system to be in an inconsistent state when processes fail concurrently. In this paper, we identify these inconsistent cases and then present a recovery algorithm to have the two benefits and ensure the system consistency when integrated with any kind of checkpointing protocol. Also, our algorithm requires no additional message compared with Elnozahy's algorithm.

A non-data aided carrier recovery technique using digital modulation format identification called multi-mode PLL (Phase Locked Loop) is proposed. This technique can be interpreted as a modulation identification method that is robust against static phase and frequency offsets. The performance of the proposed technique is studied and the analytical expressions are derived for the probability of lock detection, acquisition time over AWGN channel in the cases of M-PSK and M-QAM modulations with respect to frequency offset and signal-to-noise ratio.

Determining consistent global checkpoints of a distributed computation has applications in the areas such as rollback recovery, distributed debugging, output commit and others. Netzer and Xu introduced the notion of zigzag paths and presented necessary and sufficient conditions for a set of checkpoints to be part of a consistent global checkpoint. This result also reveals that determining the existence of zigzag paths between checkpoints is crucial for determining consistent global checkpoints. Recent research also reveals that determining zigzag paths on-line is not possible. In this paper, we present an off-line method for determining the existence of zigzag paths between checkpoints.

We propose a new dependable system called PREGMA (Platform for Reliable Environment based on a General-purpose Machine Architecture). PREGMA aims to meet two requirements -- fault tolerance and low cost -- for Internet services. It can provide fault tolerance, so we can avoid system failure and prevent data corruption, even if faults occur. That is, it masks the faults by running multiple replicated servers, each possessing its own data, in a loosely synchronized manner and delivering the majority vote as output to clients. Moreover, PREGMA is composed of COTS (Commercial Off-The-Shelf) components without modification, which makes it possible to offer the services at a low cost. We investigated two approaches for achieving redundancy of the Coordinator, which is the core of PREGMA: using the primary backup method and the active replication method. We evaluated the effectiveness of PREGMA in terms of throughput overhead, data integrity and recovery time. The results for a prototype show that PREGMA using the Coordinator with the primary backup method outperforms that with the active replication method and has throughput only 3% lower than a non-redundant system. The results also show that, in the event of failure, the recovery time is only less than one second and no data corruption occurs.

This paper proposes a packet loss recovery method using packets arrived behind the playout time for CELP (Code Excited Liner Prediction) decoding. The proposed method recovers synchronization of the filter states between encoding and decoding in the period following packet loss. The recovery is performed by replacing the degraded filter states with the ones calculated from the late arrival packet in decoding. When the proposed method is applied to the AMR (Adaptive Multi-Rate) speech decoder, it improves the segmental SNR (Signal-to-Noise Ratio) by 0.2 to 1.8 dB at packet loss rates of 2 to 10 % in case that all the packet losses occur due to their late arrival. PESQ (Perceptual Evaluation of Speech Quality) results also show that the proposed method slightly improves the speech quality. The subjective test results show that five-grade mean opinion scores are improved by 0.35 and 0.28 at a packet loss rate of 5 % at speech coding bitrates of 7.95 and 12.2 kbit/s, respectively.

Since the characteristic to current information systems is the dynamic and concurrent change of their configurations and scales with non-stop provision of their services, the system management should inevitably rely on autonomic computing. Since fault tolerance is the one of important system management issues, it should also be incorporated in autonomic computing environment. This paper argues what should be taken into consideration and what approach could be available to realize the fault tolerance in such environments.

Cluster systems are getting widely used because of good performance / cost ratio. However, their reliability has not been well discussed in practical environment so far. As the number of commodity components in a cluster system gets increased, it is indispensable to support reliability by system software. SCore cluster system software is a parallel programming environment for High Performance Computing (HPC). SCore provides checkpointing and rollback-recovery mechanism for high availability. In this paper, we analyze and evaluate the checkpointing and rollback-recovery mechanisms of SCore quantitively. The experimental results reveal that the required time for checkpointing scales very well in respect to the number of computing nodes. However, the required time is quite long due to the low effective network bandwidth. Based on the results, we modify SCore and successfully make checkpointing and recovery 1.8 2.8 times and 3.7 5.0 times faster respectively. This is very helpful for cluster systems to achieve high performance and high availability.

Multicasting is an efficient communication tool for use in multi-point applications such as conferencing and information distribution. In ad hoc networks, node mobility causes frequent changes of network topology, and re-construction of the multicast tree in an efficient and effective manner becomes a critical issues. In case of link breakage, most of the multicast tree construction protocols available presently require either a total re-build of the tree or to reconnect a disjoined node back to the multicast tree via the shortest path which may disrupt the optimising factors, such as energy consumption, delay or cost, used in the building of the original tree. In this paper, we introduce a computationally efficient recovery algorithm which will also minimise the power consumption on the tree.

Forked checkpointing scheme is proposed to achieve low checkpoint overhead. When a process wants to take a checkpoint in the forked checkpointing scheme, it creates a child process and continues its normal computation. Two recovery models can be used for forked checkpointing when the parent process fails before the child process establishes the checkpoint. One is the pessimistic recovery model where the recovery process rolls back to the previous checkpoint state. The other is the optimistic recovery model where a recovery process waits for the checkpoint to be established by the child process. In this paper, we present the recovery models for forked checkpointing by deriving the expected execution time of a process with and without checkpointing and also show that the expected recovery time of the optimistic recovery model is smaller than that of the pessimistic recovery model.

Integration of the IP/MPLS network and the WDM optical mesh network is a promising approach to realizing an efficient backbone network. Because of the great volumes of traffic carried, the social cost incurred by a failure will be extremely high, so survivability is very important in the backbone network. In survivable IP/MPLS over WDM backbone networks, cooperation of the optical level fault recovery and the IP/MPLS level fault recovery is essential. This paper analyzes cost characteristics of the optical level fault recovery and the IP/MPLS level fault recovery. A mathematical programming method is proposed to minimize the initial network cost when the IP/MPLS level fault recovery is utilized in the survivable IP/MPLS over WDM networks. Using this method, the initial network cost needed for the IP/MPLS level fault recovery is compared with that for the optical level fault recovery. The initial network cost for the LSP (Label Switched Path) protection scheme is smaller than that for the shared light-path protection scheme and larger than that for the pre-plan type light-path restoration scheme. The LSP protection scheme is suitable for the best-effort type traffic while the shared light-path protection scheme may be suitable for the bandwidth guaranteed type traffic.

Progress in WDM transmission technology and the development of optical cross-connect systems has made optical backbone networks a reality. The conventional planning methodologies for such optical backbone networks calculate optimum light-path arrangements to minimize the network cost under the condition that the number of demanded light-paths is given in advance. However, the light-path demand varies according to the light-path prices. Thus, a new planning methodology for the optical backbone networks is necessary to optimize the light-path prices and to maximize the profit obtained from the network. This paper proposes a new planning methodology for the survivable optical networks. This methodology is based on economic theory for competitive markets involving plural kinds of commodities. Using this methodology, the optimum light-path prices can be decided to maximize the obtained profit. A numerical example is presented to show that the obtained profit can be improved by preparing various light-path classes with different recovery modes and introducing an appropriate light-path pricing according to the reliability of each light-path class.

A new clock and data recovery circuit (CDR) is realized for the application of data communication systems requiring GHz-range clock signals. The high frequency jitter is one of major performance-limiting factors in CDR, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Furthermore, optical characteristics for fast locking are achieved with the adaptive delay cell in the phase detector. The circuit is designed based on CMOS 0.25 µm fabrication process and its performance is verified by measurement results.

We investigate the design of an interpolation filter of a multi-frequency time division multiple access (MF-TDMA) demodulator which is applied to digital video broadcasting-return channel system via satellite (DVB-RCS). We propose two interpolation filters for symbol timing recovery in a digital receiver where the input analog to digital conversion sampling clock is not synchronized to the transmitter symbol clock. The two proposed interpolation filters are designed by the least mean-square-error at the output of the receiver. Simulation results show that a performance improvement is achieved by employing the proposed interpolation filter.

In this paper, we present a 10 Gbase Ethernet Transceiver that is suitable for 10 Gb/s Ethernet applications. The 10 Gbase Ethernet Transceiver LSI, which contains the high-speed interface and the fully integrated IEEE 802.3ae compliant logics, is fabricated in a 0.18 µm SOI/CMOS process and dissipates 2.9 W at 1.8 V supply. By incorporating the monolithic approach and the use of the advance CMOS process, this 10 GbE transceiver realizes a low power, low cost and compact solution for the exponentially increasing need of broadband network applications.

We propose a simple technique for reducing the jitter of the output clock generated in the clock recovery circuit (CRC) for burst-mode data transmission. By using this technique, the proposed CRC based on the gated oscillator (GO) can recover the output clock with a low-jitter even when there are consecutive same data streams encountered in the system. The circuit is composed only of digital logic devices and can recover the input data errorless until 1,000 consecutive same data bits are incoming.

A blind source separation problem in a solicitations context is addressed. The mixture stems from several telecommunication signals, the symbol periods of which are unknown and possibly different. Cost functions are introduced, the optimization of which achieves the equalization for a user, i.e. estimation of the symbol period and the associated sequence of symbols. The method is iterated by implementing a deflation. The theoretical results are validated by simulations.

A simple phase detector reducing the pattern dependent jitter in clock recovery circuit is developed in this paper. The developed phase detector automatically aligns the recovered to clock in the center of the data eye, while producing no ripple to the control voltage in locked condition of the PLL based clock recovery circuit. The UP and DOWN signals are separately generated to align them in locked condition. Thus, no explicit transient waveforms do not exist at the output of the phase detector. The elimination of high frequency ripple improves the jitter characteristics of the clock recovery circuit. The delay unit used in our phase detector requires no accurate control of the delay time. This feature eliminates the use of DLL to generate the precise delay time, which reduce the power consumption and area of the phase detector. The simulation shows that the RMS timing jitter is reduced by more than four times when compared with the conventional scheme. The rms jitter is 32 ps for the proposed phase detector and 133 ps for the phase detector in conventional scheme. In conventional scheme, even when the lock is achieved, the phase detector produces a triwave transient on the control voltage of the VCO, which depends on the data pattern. In the proposed phase detector, no such transient waveforms do not exist. The proposed phase detector can be incorporated in high performance clock recovery circuit for data communication systems.

The present study introduces the adaptive BPF to the BPSK coherent detection system and the characteristic of the resulting system is investigated.