A clock recovery circuit is a key component in optical communication systems. In this paper, an optoelectronic clock recovery circuit is reported that monolithically integrates a resonant tunneling diode (RTD) and a uni-traveling-carrier photodiode (UTC-PD). The circuit is an injection-locked-type RTD oscillator that uses the photo-current generated by the UTC-PD. Fundamental and sub-harmonic clock extraction is confirmed for the first time with good clock recovery circuit characteristics. The IC extracts an electrical 11.55-GHz clock signal from 11.55-Gbit/s RZ optical data streams with the wide locking range of 450 MHz and low power dissipation of 1.3 mW. Furthermore, the extraction of a sub-harmonic clock from 23.1-Gbit/s and 46.2-Gbit/s input data streams is also confirmed in the wider locking range of 600 MHz. The RMS jitter as determined from a single sideband phase noise measurement is extremely low at less than 200 fs in both cases of clock and sub-harmonic clock extraction. To our knowledge, the product of the output power and operating frequency of the circuit is the highest ever reported for injection-locked-type RTD oscillators. These characteristics indicate the feasibility of the optoelectronic clock recovery circuit for use in future ultra-high-speed fully monolithic receivers.

We propose a new bit timing recovery (BTR) scheme, called perturbed sampling BTR (PSBTR), that can operate near the symbol rate in high-bit-rate wireless systems. A peculiar sample clock, the duty factor of which is not 50%, is used in the PSBTR scheme. We call this type of clock a perturbed sample clock and use it for clock recovery. In PSBTR, there is no cycle slip of the sample clock, and the PSBTR circuit is mostly digital. We examine the performance of the PSBTR scheme under additive white Gaussian noise (AWGN) by computer simulation and experiment, and from these results, clarify the relationship between the performance and circuit parameters of the PSBTR circuit. The overall results indicate that the PSBTR scheme performs well and can be employed as a BTR scheme for high-bit-rate wireless systems.

A clock recovery circuit is a key component in optical communication systems. In this paper, an optoelectronic clock recovery circuit is reported that monolithically integrates a resonant tunneling diode (RTD) and a uni-traveling-carrier photodiode (UTC-PD). The circuit is an injection-locked-type RTD oscillator that uses the photo-current generated by the UTC-PD. Fundamental and sub-harmonic clock extraction is confirmed for the first time with good clock recovery circuit characteristics. The IC extracts an electrical 11.55-GHz clock signal from 11.55-Gbit/s RZ optical data streams with the wide locking range of 450 MHz and low power dissipation of 1.3 mW. Furthermore, the extraction of a sub-harmonic clock from 23.1-Gbit/s and 46.2-Gbit/s input data streams is also confirmed in the wider locking range of 600 MHz. The RMS jitter as determined from a single sideband phase noise measurement is extremely low at less than 200 fs in both cases of clock and sub-harmonic clock extraction. To our knowledge, the product of the output power and operating frequency of the circuit is the highest ever reported for injection-locked-type RTD oscillators. These characteristics indicate the feasibility of the optoelectronic clock recovery circuit for use in future ultra-high-speed fully monolithic receivers.

This study is aimed to explore a fast convergence method of blind equalization using higher order statistics (cumulants). The efforts are focused on deriving new theoretical solutions for blind equalizers rather than investigating practical algorithms. Under the common assumptions for this framework, it is found that the condition for blind equalization is directly associated with an eigenproblem, i. e. the lag coefficients of the equalizer can be obtained from the eigenvectors of a higher order statistics matrix. A method of blind phase recovery is also proposed for QAM systems. Computer simulations show that very fast convergence can be achieved based on the approach.

The characteristics of the decision feedback carrier recovery loop (DFL) for conventional QPSK signaling is evaluated experimentally through measurements of the carrier-to-noise ratio of the regenerated carrier, lock range, acquisition waveforms and bit error rates. The results show that the DFL hardly exhibits inferiority to the ideal synchronization by designing the loop natural frequency adequately small. The DFL is shown superb in carrier tracking.

In this paper an analysis on the oversampling data recovery circuit is presented. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance. Theoretical analysis enables us to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the oversampling data recovery circuit for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10-11 BER, 8 times oversampling has about 2 dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits depending on the input data rate and input noise. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5 dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling in white noise dominant input data. The results were applied to the fabricated circuits to validate the analysis.

We proposed Reversible Energy Recovery Logic (RERL) using an 8-phase clocking scheme, which is a dual-rail reversible adiabatic logic for ultra-low-energy applications. Because we eliminated non-adiabatic energy loss in RERL by using the concept of reversible logic, RERL has only adiabatic and leakage losses. In this paper we explain its operation and logic design and present its simulation and experimental results. We also present an energy-efficient 8-phase, clocked power generator that uses an off-chip inductor. With simulation results for the full adder, we confirmed that the RERL circuit consumed substantially less energy than other logic circuits at low-speed operation. We evaluated a test chip implemented with a 0.6-µm CMOS technology, which integrated a chain of inverters with a clocked power generator. In the experimental results, the RERL circuit consumed only 4.5% of the dissipated energy of a static CMOS circuit at an optimal operating speed of 40 kHz. In conclusion, RERL is suitable for the applications that do not require high performance but low-energy consumption because its energy consumption can be decreased to the minimum by reducing the operating frequency until adiabatic and leakage losses are equal.

Acquisition of three-dimensional information of a real-world scene from two-dimensional images has been one of the most important issues in computer vision and image understanding in the last two decades. Noncontact range acquisition techniques can be essentially classified into two classes: Passive and active. This paper concentrates on passive depth extraction techniques which have the advantage that 3-D information can be obtained without affecting the scene. Passive range sensing techniques are often referred to as shape-from-x, where x is one of visual cues such as shading, texture, contour, focus, stereo, and motion. These techniques produce 2.5-D representations of visible surfaces. This survey discusses aspects of this research field and reviews some recent advances including video-rate range imaging sensors as well as emerging themes and applications.

The clock recovery circuit is a key component in high-speed electrical time-division multiplexing (ETDM) transmission systems. In the case of clock extraction from non-return-to-zero (NRZ) signals, differentiation and full-wave rectification are indispensable. Exclusive OR/NOR circuits (XOR) are widely used for this purpose. In this paper, we describe an XOR IC fabricated with 0. 1-µm gate-length InAlAs/InGaAs/InP HEMTs for a 40-Gbit/s class clock recovery circuit. The IC was configured with a symmetrical Gilbert cell type XOR gate and two types of peaking techniques are used to achieve its high bit-rate. On-wafer-measurements indicate that the IC operates as fast as 80 Gbit/s and can extract a 40-GHz frequency component from 40-Gbit/s NRZ input signals. To confirm the feasibility of using the packaged XOR IC in clock recovery circuits, the conversion gain of the IC, which was operated as a differentiater and full-wave rectifier, was evaluated. Assuming that the input to the clock recovery circuit is a 1 Vp-p signal, the relatively high output power of -17 dBm can be obtained with low dependency on the length of the input pseudo-random bit streams. Furthermore, a clock recovery circuit was assembled using the packaged XOR IC, a waveguide filter and a commercial amplifier; it offers the practical system-bit-rate of 39. 81312 GHz with the low rms jitter of 900 fs.

This paper proposes a novel sequential coherent preambleless demodulator that uses phase signals instead of complex signals in the automatic frequency control (AFC) and carrier recovery circuits. The proposed demodulator employs a phase-combined frequency error detection circuit and dual loop AFC circuit to achieve fast frequency acquisition and low frequency jitter. It also adopts an open loop carrier recovery scheme with a sample hold circuit after the carrier filter to ensure carrier signal stability within a packet. It is shown that the frame error rate performance of the proposed demodulator is superior, by 30%, to that offered by differential detection in a frequency selective Rayleigh fading channel. The hardware size of the proposed demodulator is about only 1/10 that of a conventional coherent demodulator employing complex signals.

Although threshold key-recovery systems for the discrete log based cryptosystems such as the ElGamal scheme have been proposed by Feldman and Pedersen , no (practical) threshold key-recovery system for the factoring based cryptosystems such as the RSA scheme has been proposed. This paper proposes the first (practical) threshold key-recovery systems for the factoring based cryptosystems including the RSA and Rabin schemes. Almost all of the proposed systems are unconditionally secure, since the systems utilize unconditionally secure bit-commitment protocols and unconditionally secure VSS.

We present a receiver structure with joint blind equalization, carrier recovery, and timing recovery. The blind equalizer employs a decomposition transversal filtering technique which can reduce the complexity of convolution to about a half. We analyze the performance surface of the equalizer cost function and show that the global minima correspond to perfect equalization. We also derive proper initial tap settings of the equalizer for convergence to the global minima. We describe the timing recovery and the carrier recovery methods employed. And we describe a startup sequence to bring the receiver into full operation. The adaptation algorithms for equalization, carrier recovery, and timing recovery are relatively independent, resulting in good operational stability of the overall receiver. Some simulation results for cable-modem type of transmission are presented.

A novel image improving algorithm for compressed image sequence by merging a reference image is presented. A high quality still image of the same scene is used as a reference image. The degraded images are improved by merging reference image with them. Merging amount is controlled by the resemblance between the reference image and compressed image after applying motion compensation. Experiments conducted on sequences of JPEG images are given. This technique does not need a prior knowledge of compression technique so it can be applied to other techniques as well.

Since most digital phase-locked loops (DPLLs) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady-state, the DPLL loop bandwidth is preferred to being adjusted accordingly. In this paper, a bandwidth adjusting (adaptive) algorithm is presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardware requirement. This algorithm, based on the recursive least squares (RLS) criterion, suggest an optimal sequence of control parameters for a dual-loop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant. The algorithm can be used for carrier recovery or clock recovery in mobile communications, local area networks and disk drivers that require a short initial preamble period.

In this paper, a transceiver VLSI architecture is proposed for high speed digital CATV modems, which can perform both the QAM and the VSB transmissions. The proposed architecture of all-digital dual-mode QAM/VSB receiver consists of digital AGC, digital demodulator, fractionally spaced blind equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture can achieve an SNR 29 dB for both the 64-QAM mode and 8-VSB mode when the 10 bit ADC input signal SNR is 36 dB, and there are 6 kHz of carrier frequency offset, 110 ppm of symbol rate offset, and -82 dBc carrier phase-jitter at 10 kHz away from the nominal carrier frequency.

As the current Internet becomes popular in information access, demands for real-time display and playback of continuous media are ever increasing. The applications include real-time audio/video clips embedded in WWW, electronic commerce, and video-on-demand. In this paper, we present a new control protocol R3CP for real-time applications that transmit stored MPEG video stream over a lossy and best-effort based network environment like the Internet. Several control mechanisms are used: a) packet framing based on the meta data; b) adaptive queue-length based rate control scheme; c) data preloading; and d) look-ahead pre-retransmission for lost packet recovery. Different from many adaptive rate control schemes proposed in the past, the proposed flow control is to ensure continuous, periodic playback of video frames by keeping the receiver buffer queue length at a target value to minimize the probability that player finds an empty buffer. Contrary to the widespread belief that "Retransmission of lost packets is unnecessary for real-time applications," we show the effective use of combining look-ahead pre-retransmission control with proper data preloading and adaptive rate control scheme to improve the real-time playback performance. The performance of the proposed protocol is studied via simulation using actual video traces and actual delay traces collected from the Internet. The simulation results show that R3CP can significantly improve frame playback performance especially for transmission paths with poor packet delivery condition.

A key distribution system is a system in which users securely generate a common key. One kind of identity-based key distribution system was proposed by E. Okamoto. Its security depends on the difficulty of factoring a composite number of two large primes like RSA public-key cryptosystem. Another kind of identity-based key distribution system was proposed by K. Nyberg, R. A. Rueppel. Its security depends on the difficulty of the discrete logarithm problem. On the other hand, Koblitz and Miller described how a group of points on an elliptic curve over a finite field can be used to construct a public key cryptosystem. In 1997, we proposed an ID-based key distribution system over an elliptic curve, as well as those over the ring Z/nZ. Its security depends on the difficulty of factoring a composite number of two large primes. We showed that this system over an elliptic curve is more suitable for the implementation than those over the ring Z/nZ. In this paper, we apply the Nyberg-Rueppel ID-based key distribution system to an elliptic curve. It provides relatively small block size and high security. This public key distribution system can be efficiently implemented. However the Nyberg-Rueppel's scheme requires relatively large data transmission. As a solution to this problem, we improve the scheme. This improved scheme is very efficient since data transferred for the common key generation is reduced to half of those in the Nyberg-Rueppel's scheme.

We introduce an image contour clustering method based on a multiscale image representation and its application to image compression. Multiscale gradient planes are obtained from the mean squared sum of 2D wavelet transform of an image. The decay on the multiscale gradient planes across scales depends on the Lipshitz exponent. Since the Lipshitz exponent indicates the spatial differentiability of an image, the multiscale gradient planes represent smoothness or sharpness around edges on image contours. We apply vector quatization to the multiscale gradient planes at contours, and cluster the contours in terms of represntative vectors in VQ. Since the multiscale gradient planes indicate the Lipshitz exponents, the image contours are clustered according to its gradients and Lipshitz exponents. Moreover, we present an image recovery algorithm to the multiscale gradient planes, and we achieve the skech-based image compression by the vector quantization on the multiscale gradient planes.

This paper proposes a new approach to recover the sign of local surface curvature of object from three shading images using neural network. The RBF (Radial Basis Function) neural network is used to learn the mapping of three image irradiances to the position on a sphere. Then, the learned neural network maps the image irradiances at the neighbor pixels of the test object taken from three illuminating directions of light sources onto the sphere images taken under the same illuminating condition. Using the property that basic six kinds of surface curvature has the different relative locations of the local five points mapped on the sphere, not only the Gaussian curvature but also the kind of curvature is directly recovered locally from the relation of the locations on the mapped points on the sphere without knowing the values of surface gradient for each point. Further, two step neural networks which combines the forward mapping and its inverse mapping one can be used to get the local confidence estimate for the obtained results. The entire approach is non-parametric, empirical in that no explicit assumptions are made about light source directions or surface reflectance. Results are demonstrated by the experiments for real images.

The adaptive associative memory proposed by Ma is used to construct a new model of semantic network, referred to as associative semantic memory (ASM). The main novelty is its computational effectiveness which is an important issue in knowledge representation; the ASM can do inference based on large conceptual hierarchies extremely fast-in time that does not increase with the size of conceptual hierarchies. This performance cannot be realized by any existing systems. In addition, ASM has a simple and easily understandable architecture and is flexible in the sense that modifying knowledge can easily be done using one-shot relearning and the generalization of knowledge is a basic system property. Theoretical analyses are given in general case to guarantee that ASM can flawlessly infer via pattern segmentation and recovery which are the two basic functions that the adaptive associative memory has.