A new electron-beam wafer inspection system has been developed. The system has a resolution of 5 nm or better, and is applicable to quarter-micron devices such as 256 Mbit DRAMs. The most remarkable feature of this system is that a specimen stage is built in the objective lens and allows a working distance (WD) of 0. "WD=0"minimizes the effect of lens aberrations, and maximizes the resolving power. Innovative designs to achieve WD=0 are as follows: (1)A large objective lens of 730-mm width 730-mm depth 620-mm height that serves as a specimen chamber, has been developed. (2)A hollow specimen stage made of non-magnetic materials has been developed.It allows the lower pole piece and magnetic coile of the objective lens inside it. (3)Acoustic motors made of non-magnetic materials are em-ployed for use in vacuum.

Many ATM switching modules with high performance have been proposed and analyzed. A development of a large scale ATM switching system (e.g., used as a central switch) is the key to realization of the broadband ISDN. However, the dimension of ATM switching ICs is limited by the technological and physical constraints on VLSI. A multistage switching configuration is one of the promising configurations for a large scale ATM switch. In this paper, we treat a 3-stage switching configuration with no internal bufferes; i.e., bufferless switches are employed at the first and second stages, and output buffered switches at the third stage. A short-term cell loss probability is analyzed in order to examine the influence of bursty traffic on performance of the bufferless switch used at the first two stages. Furthermore, we propose a 4-stage switching configuration with traffic distributors added at the first stage. This switch provides more paths between a pair of input and output ports than the 3-stage switching configuration mentioned above. A few schemes to distribute cells are compared. It is shown that the distributor successfully reduces the deterioration of cell loss probability due to bursty traffic by splitting incoming cells into several switching modules.

Throughout the paper, the proper operating of the self-routing principle in 2-D shuffle multistage interconnection networks (MINs) is analysed. (The notation 1-D MIN and 2-D MIN is applied for a MIN which interconnects 1-D and 2-D data, respectively.) Two different methods for self-routing in 2-D shuffle MINs are presented: (1) The application of self-routing in 1-D MINs by a switch-pattern preserving transformation of 1-D shuffle stages into 2-D shuffle stages (and vice versa) and (2) the general concept of self-routing in 2-D shuffle MINs based on self-routing with regard to each coordinate which is the original contribution of the paper. Several examples are provided which make the various problems transparent.

In this paper we propose a two-stage address coding scheme to transmit two data symbols at once within a frame in a MFSK/FH-CDMA system. We compare it with the conventional system using single-stage address coding. Assumed that the address codes of all users are known in the receiver. A multiuser detection scheme is applied and the performance is evaluated by computer simulations to show the improvement in bit error rate (BER) compairing to the conventional system. We also investigate the performance of error-correcting coding and decoding in the two-stage address coded MFSK/FH-CDMA system. An erasure decoding scheme is modified for the two-stage address coded system and is utilized to improve spectral efficiency or to increase user capacity in the MFSK/FH-CDMA system. Finally, we investigate a hybrid scheme of combining the multi-user detection scheme and the error-correcting decoding scheme for the two-stage address coded MFSK/FH-CDMA system. The performance is evaluated by computer simulations.

A multi-stage noise-shaping (MASH) A/D converter combining an RC-integrator and a digital correction technique for high accuracy is described. Using 1.2-µm BiCMOS technology, we developed an A/D converter for digital audio with an S/N ratio of over 100 dB. This paper discusses the principles of MASH technology with an RC-integrator, the technique for correcting RC variation, and the experimental results obtained with a fabricated chip.

This paper describes the circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for consumer video products, such as high-definition TV sets. Triple-stage conversion scheme combined with two new conversion methods, "Dynamic Sliding Reference Method" and "Triangular Interpolation Method," and an internal Bi-CMOS Sample/Hold circuit have been developed. These conversion methods require no adjustment circuit to fit reference voltages between conversion stages and realize small active area. As a result, a maximum conversion frequency of 16 MHz, acceptable SNRs of 56 dB and 48 dB for 10 kHz and 8 MHz input frequency respectively and small DNLE of 0.75 LSB have been achieved. This ADC is fabricated with 1.2 µm Bi-CMOS technology and integrates very small number of bipolar transistors of 2 K on a small active area of 2.52.7 mm2 and consumes 350 mW.

The double-stage threshold-type foreground-background congestion control for the common-store queueing system with multiple nonpreemptive priority classes is proposed to improve the transient performance, where the numbers of accepted priority packets in both foreground and background stores are controlled under the double-stage threshold-type scheduling. In the double-stage threshold-type congestion control, the background store is used for any priority packets, and some parts of the background store are reserved for lower-priority packets to accommodate more lower-priority packets in the background store, whereas some parts of the foreground store are reserved for higher-priority packets to avoid the priority deadlock. First, we derive the general set of coupled differential equations describing the system-state, and the expressions for mean system occupancy, throughput and loss probability. Second, the transient behavior of system performance is evaluated from the time-dependent state probabilities by using the Runge-Kutta procedure. It is shown that when the particular traffic class becomes overloaded, high throughputs and low loss probabilities of other priority classes can be obtained.

Throughout the paper, the nearest-neighbour (NN) interconnection of switches within a multistage interconnection network (MIN) is analysed. Three main results are obtained: (1) The switch preserving transformation of a 2-D MIN into the 1-D MIN (and vice versa) (2) The rearrangeability of the MIN and (3) The number of stages (NS) for the rearrangeable nonblocking interconnection. The analysis is extended to any dimension of the interconnected data set. The topological equivalence between 1-D MINs with NN interconnections (NN-MINs) and 1-D cellular arrays is shown.

This paper presents a cost-effective network for very large ATM cross-connects. In order to develop it, we propose the delta network with expanded middle stages. This proposed network is the intermediate network between a nonblocking network and the delta network with respect to the cost of hardware and internal blocking probability. Using this network, we explore the tradeoff between the cost and internal blocking probability, and derive the optimum configuration under temporarily deviating traffic. Internal blocking occurs when input traffic temporarily deviates from its average value. However, we cannot evaluate the internal blocking probability by using conventional traffic models. In this paper, we adopt temporarily deviating traffic such that all traffic is described as the superposition of the paths which are defined by traffic parameters. As can easily be seen, the path corresponds to virtual path (VP) or virtual channel (VC). Therefore, we believe that our model describes actual traffic more exactly than conventional models do. We show that the optimum configuration is the proposed network whose expansion ratio γ=3 when the maximum number of paths that can be accommodated in one link is greater than 22. This network achieves the internal blocking probability of 10-10. As an example of this network, we show that the proposed network of size 7272 is constructed with only 40% of the hardware required by the nonblocking network.

It is desirable to design an ATM switch that is nonblocking at the connection level by using simple connection admission control (CAC) schemes. To accomplish this goal, it is necessary to consider the relationships between CAC, cell-level quality-of-services (QOS), and the structure of multistage switches as well as switch modules. In this paper, we formulate a framework to design a multistage nonblocking ATM switch. We show that if a switch has the property of the Sufficiency of Knowledge of External Loads (SKEL), i.e., the property that its cell-level performance is robust to the distribution of incoming traffic among all inputs, then the switch is also nonblocking at the connection-level by using a simplified CAC that guarantees QOS of a connection by controlling the aggregate loads on outputs. Furthermore, we show that a Clos three-stage network using SKEL switch modules and Multipath Self-Routing (MPSR) also has the SKEL property and is a nonblocking switching network that needs CAC only at its outputs. We also demonstrate a design of multistage nonblocking ATM switches with Knockout switch modules.

In this paper we estimate the number of permutations realizable in fault-tolerant multistage interconnection networks designed to tolerate faults on any switching element. The Parallel Omega network and the INDRA network are representative types of fault-tolerate multistage interconnection networks designed to tolerate a single fault. In order to evaluate the enhancement in the function of network by preparing the hardware redundancy for fault-tolerance, we estimate the number of permutations realizable in fault-tolerant networks. This result enables us to set up a standard to evaluate the hardware redundancy required to tolerate multifaults from the viewpoint of the enhancement of network function. This paper concludes that in the case where the number of inputs is up to 32 the increase ratio of the number of realizable permutations is no more than 1/0.73 even if the tolerance to multifaults is prepared instead of the tolerance to a single fault.

A new recursive method for obtaining the mean waiting time in a polling system with general service order and gated service discipline is proposed. The analytical approach used to obtain the mean waiting time is via an imbedded Markov chain and a new recursive method is used to obtain the moments of pseudocycle time which are parameters in the formula for the mean waiting time. This method is computationally tractable, so the analytical results can cover a wide range of applications. Simulations are also conducted to verify the validity of the analysis.

This paper describes a new free-space optical switch structure based on cascaded beam shifters (each consists of a liquid-crystal polarization controller array and a birefringent plate). This structure comprises 2-input, 2-output switching elements that are locally connected by links. It is applicable to a variety of switching networks, such as a Clos network. The switching network based on this structure is an analog switch that is transparent to signal format, bit rate, and modulation type, so it can handle various types of optical signals. Theoretical feasibility studies indicate that compact large-scale switches (i.e., 100-1000 ports) with relay lens systems can be implemented using beam shifters with a 0.4-dB insertion loss and a 30-dB extinction ratio. Experimental feasibility studies indicate that a 1024-cell beam shifter module with a 0.5-dB insertion loss and a 23-dB extinction ratio is possible at present. An alignment-free assembly technique using precise alignment guides is also confirmed. An experimental 8-stage, 1024-input 256-output concentrator shows low insertion loss characteristics (6.8dB on average) owing to the low-loss beam shifters and the alignment-free assembly technique. Practical switching networks mainly require the improvement of the extinction ratio of the beam shifter module and the development of a fiber pig-tailing technique. This switch structure is applicable to transparent switching networks such as subscriber line concentrators and inter-module connectors.

The design of a high speed self-routing network switch module is described. Clock distribution and timing design to achieve high-speed operation are considered. A 88-port self-routing Benes network switch prototype on multi-chip module is fabricated using 44-port space division switch LSIs. The switch module achieves a maximum measured clock frequency of 750MHz under switching operation. Resultant total throughput of the switch module is 12Gbit/s.

Three dimensional (3-D) optics offers potential advantages to the massively-parallel systems over electronics from the view point of information transfer. The purpose of this paper is to survey some aspects of the 3-D optical interconnection technology for the future massively-parallel computing systems. At first, the state-of-art of the current optoelectronic array devices to build the interconnection networks are described, with emphasis on those based on the semiconductor technology. Next, the principles, basic architectures, several examples of the 3-D optical interconnection systems in neural networks and multiprocessor systems are described. Finally, the issues that are needed to be solved for putting such technology into practical use are summarized.

MISRs are widely used as signature circuits for VLSI built-in self tests. To improve the aliasing probability of MISRs, multiple MISRs and M-stage MISRs with m inputs are available, where M is grater than m. The aliasing probability as a function of the test length is analyzed for the compaction circuits for a binary symmetric channel. It is observed that the peak aliasing probability of the double MISRs is less than that of M-stage MISRs with m inputs. It is also shown that the final aliasing probability for a multiple MISR with d MISRs is 2dm and that for an M-stage MISR with m imputs is 2M if it is characterized by a primitive polynomial.

ATM cross-connect systems, which will be used for provisioning virtual paths (i.e. logical direct connections between exchanges) in future broadband transport networks, simplify network configuration and yield increased routing and capacity allocating flexibility. This paper describes the design of a large capacity ATM cross-connect system that has a multi-stage network structure which requires only one type of switch module. The capacity of the proposed system can be easily increased without service interruptions. To realize cell sequence integrity, a time stamp is added to the self-routing tag. Required time stamp length and efficient module size are discussed.