Channel coding for bandwidth limited channels based on multilevel bit-interleaved channels is discussed in this paper. This coding and decoding structure has the advantage of simplified design, and naturally incorporates flexible and powerful design of unequal error protection (UEP) capabilities, especially over time-varying channels to be often found in mobile radio communications. Multilevel coded modulation with multistage decoding, and bit-interleaved coded modulation are special cases of the proposed general framework. Simulation results verify the usefulness of the system considered.

In this paper, we investigate multilevel coding and multistage decoding for satellite broadcasting with moderate decoding complexity. An unconventional signal set partitioning is used to achieve unequal error protection capabilities. Two possibilities are shown and analyzed for practical systems: (i) linear block component codes with near optimum decoding, (ii) punctured convolutional component codes with a common trellis structure.

This paper deals with the prediction of stock trends by using the wavelet transform and the multi-stage fuzzy inference system based upon the optimization of membership function by using the GA. The system is expected to recognize the short-term feature which is usually used to estimate the rise/fall of price by human experts. In the prediction of stock prices, the wavelet transform is used to describe the short term feature of the stock trend. The fractal dimension and the variance of the time series are also used as the input variables. By dividing the inference system into multiple stages, the total number of rules is sufficiently depressed compared to the single stage system. In each stage of inference only a portion of input variables are used as the input, and output of the stage is treated as an input to the next stage. To give better performance, the shape of the membership function of the inference rules is optimized by using the GA. Each individual corresponds to an inference system, and its fitness is calculated as the ratio of the correct recognition. In the simulation study, we define the rise and fall of prices by considering the threshold value for the price change, and the interval of prediction. Then, the parameters of the system are adjusted by using the data for learning and the performance is evaluated by comparing the prediction and observation. The simulation study shows that the inference system gives about a 70% correct prediction of the price change of stocks. The result is compared to the prediction by the neural network, and we see better classification of the fuzzy system.

This paper describes a distributed traffic control scheme for large multi-stage ATM switching systems. When a new virtual circuit is to be added from some source line-interface unit (LU) to a destination LU, the system must find an optimal path through the system to accommodate the new circuit. Conventional systems have a central control processor and control lines to manage the bandwidth of all the links in the systems. The central control processor handles all the virtual circuits, but have trouble doing this when the switching system becomes large because of the limited ability of the central processor to handle the number of virtual circuits. A large switching system with Tbit/s-class throughput requires a distributed traffic control scheme. In our proposed switching system, each port of the basic switches has its own traffic monitor. Operation, administration, and maintenance (OAM) cells that are defined inside the system carry the path-congestion information to the LUs, enabling each LU to route new virtual circuits independently. A central control processor and control lines are not required. The performance of the proposed system depends on the interval between OAM cells. This paper shows how an optimal interval can be determined in order to maximize the bandwidth for user cells. This traffic control scheme will suit future Tbit/s ATM switching systems.

This paper shows the design of multi-stage fuzzy inference system with smaller number of rules based upon the optimization of rules by using the genetic algorithm. Since the number of rules of fuzzy inference system increases exponentially in proportion to the number of input variables powered by the number of membership function, it is preferred to divide the inference system into several stages (multi-stage fuzzy inference system) and decrease the number of rules compared to the single stage system. In each stage of inference only a portion of input variables are used as the input, and the output of the stage is treated as an input to the next stage. If we use the simplified inference scheme and assume the shape of membership function is given, the same backpropagation algorithm is available to optimize the weight of each rule as is usually used in the single stage inference system. On the other hand, the shape of the membership function is optimized by using the GA (genetic algorithm) where the characteristics of the membership function is represented as a set of string to which the crossover and mutation operation is applied. By combining the backpropagation algorithm and the GA, we have a comprehensive optimization scheme of learning for the multi-stage fuzzy inference system. The inference system is applied to the automatic bond rating based upon the financial ratios obtained from the financial statement by using the prescribed evaluation of rating published by the rating institution. As a result, we have similar performance of the multi-stage fuzzy inference system as the single stage system with remarkably smaller number of rules.

The architecture and control procedure for a direct conversion receiver are investigated for a linear modulation scheme. The proposed design techniques maintain receiver linearity despite various types of signal distortion. The techniques include the fast gain control procedure for receiving a control channel for air interface connection, DC offset canceling in both analog and digital stages, and 2nd-order intermodulation distortion canceling in an analog down-conversion stage. Experimental and computer simulation results on PHS (Personal Handy-phone System) parameters, showed that required linear modulation performance was achieved and thus the applicability of the proposed techniques was demonstrated.

This paper proposesd a non-blocking multi-stage ATM switch based on a hierarchical-cell-resequencing (HCR) mechanism and high-speed WDM interconnection and reports on its feasibility study. In a multi-stage ATM switch, cell-based routing is effective to make the switch non-blocking, because all traffic is randomly distributed over intermediate switching stages. But due to the multi-path conditions, cells may arrive out of sequence at the output of the switching fabric. Therefore, resequencing must be performed either at each output of the final switching stage or at the output of each switching stage. The basic HCR switch performs cell resequencing in a hierarchical manner when switching cells from an input-lines to a output-line. As a result, the cell sequence in each output of the basic HCR switch is recovered. A multi-stage HCR switch is constructed by interconnecting the input-lines and output-lines of these basic HCR switches in a hierarchical manner. Therefore, the cell sequence in each final output of the switching fabric is conserved in a hierarchical manner. In this way, cell-based routing becomes possible and a multi-stage ATM switch with the HCR mechanism can achieve 100% throughput without any internal speed-up techniques. Because a large-capacity multi-stage HCR switch needs a huge number of high-speed signal interconnections, a breakthrough in compact optical interconnection technology is required. Therefore, this paper proposes a WDM interconnection system with an optical router arrayed waveguide filter (AWGF) that interconnects high-speed switch elements effectively and reports its feasibility study. In this architecture, each switch element is addressed by a unique wavelength. As a result, a switch in a previous stage can transmit a cell to any switch in the next stage by only selecting its cell transmission wavelength. To make this system feasible, we developed a wide-channel-spacing optical router AWGF and compact 10-Gbit/s optical transmitter and receiver modules with a compact high-power electroabsorption distributed feedback (EA-DFB) laser and a new bit decision circuit. Using these modules, we confirmed stable operation of the WDM interconnection. This switch architecture and WDM interconnection system should enable the development of high-speed ATM switching systems that can achieve throughput of over 1 Tbit/s.

Design and evaluation of a high-performance switch architecture for free-space photonic switching systems is described. The switch is constructed of 22 switching elements and employs special multistage interconnection patterns. The connection setup algorithm and the control procedure at the switching elements are based on a "rerouting algorithm."" Performance analysis shows that the blocking probability of the switch is easily controlled by increasing the number of switching stages. Example implementations of this switch are shown in which birefringent plates, polarization controllers, etc. are used.

Design and evaluation of a high-performance switch architecture for free-space photonic switching systems is described. The switch is constructed of 22 switching elements and employs special multistage interconnection patterns. The connection setup algorithm and the control procedure at the switching elements are based on a "rerouting algorithm." Performance analysis shows that the blocking probability of the switch is easily controlled by increasing the number of switching stages. Example implementations of this switch are shown in which birefringent plates, polarization controllers, etc. are used.

This paper proposesd a non-blocking multi-stage ATM switch based on a hierarchical-cell-resequencing (HCR) mechanism and high-speed WDM interconnection and reports on its feasibility study. In a multi-stage ATM switch, cell-based routing is effective to make the switch non-blocking, because all traffic is randomly distributed over intermediate switching stages. But due to the multi-path conditions, cells may arrive out of sequence at the output of the switching fabric. Therefore, resequencing must be performed either at each output of the final switching stage or at the output of each switching stage. The basic HCR switch performs cell resequencing in a hierarchical manner when switching cells from an input-lines to a output-line. As a result, the cell sequence in each output of the basic HCR switch is recovered. A multi-stage HCR switch is constructed by interconnecting the input-lines and output-lines of these basic HCR switches in a hierarchical manner. Therefore, the cell sequence in each final output of the switching fabric is conserved in a hierarchical manner. In this way, cell-based routing becomes possible and a multi-stage ATM switch with the HCR mechanism can achieve 100% throughput without any internal speed-up techniques. Because a large-capacity multi-stage HCR switch needs a huge number of high-speed signal interconnections, a breakthrough in compact optical interconnection technology is required. Therefore, this paper proposes a WDM interconnection system with an optical router arrayed waveguide filter (AWGF) that interconnects high-speed switch elements effectively and reports its feasibility study. In this architecture, each switch element is addressed by a unique wavelength. As a result, a switch in a previous stage can transmit a cell to any switch in the next stage by only selecting its cell transmission wavelength. To make this system feasible, we developed a wide-channel-spacing optical router AWGF and compact 10-Gbit/s optical transmitter and receiver modules with a compact high-power electroabsorption distributed feedback (EA-DFB) laser and a new bit decision circuit. Using these modules, we confirmed stable operation of the WDM interconnection. This switch architecture and WDM interconnection system should enable the development of high-speed ATM switching systems that can achieve throughput of over 1 Tbit/s.

Unequal error protection (UEP) is a very promising coding technique for satellite broadcasting, as it gradually reduces the transmission rate. From the viewpoint of bandwidth efficiency, UEP should be achieved in the context of multilevel coded modulation. However, the conventional mapping between encoded bits and modulation signals, usually realized for multilevel block modulation codes and multistage decoding, is not very compatible with UEP coding because of the large number of resulting nearest neighbor codewords. In this paper, new coded modulation schemes for UEP based on unconventional partitioning are proposed. A linear operation referred to as interlevel combination is introduced. This operation generalizes previous partitioning proposed for UEP applications and provides additional flexibility with respect to UEP capabilities. The error performance of the proposed codes are evaluated both by computer simulations and a theoretical analysis. The obtained results show that the proposed codes achieve good tradeoff between the proportion and the error performance of each error protection level.

This paper describes a calculation method of large-signal characteristics of multi-stage power amplifier modules using source-pull and load-pull data. An output power, a power-added efficiency, and a phase deviation of multi-stage power amplifier modules are calculated based on the source-pull and load-pull data, which are comprised of input and output reflection coefficients, an input power, an output power, a phase deviation and a drain voltage and current, taking into account the source and load impedance of each stage FET. Applying this method to a 900 MHz two-stage Si-MOSFET power amplifier module, the calculated and measured results are in good agreement.

In the future asynchronous transfer mode (ATM) networks, an efficient virtual path (VP) control strategy must be applied to guarantee the network has high throughput with tolerable node processing load. The multistage VP control may be the best candidate since the tasks in this method are shared by the central node and local nodes, and it allows us to track the traffic changes while maintain a good state of the VP topology by reconfiguring it at regular or need based intervals. In this paper, we focus on the VP topology optimization problem in the multistage VP control. We first present the problem formulation in which the tradeoff between the network throughput and processing costs is considered, and then employ an algorithm based on a route-neuron Hopfield neural network (HNN) model to solve this problem. The numerical results demonstrate the HNN can converge to optimal solutions with high probability and stability while in other cases to near optimal solutions if the values of the system parameters in the route-neuron model are chosen according to some empirical formulas provided in this paper.

In this paper, we propose an interference canceller for asynchronous DS-CDMA. The principle is based on parallel cancellation using soft decision(PCSD), however, we propose to add an operation to suppress the strength of interfering signals replica on PCSD. We show here that this operation plays a very important theoretical role in PCSD, and that the performance of our proposed scheme approaches that of a perfect decorrelating detector under certain conditions. With this theoretical background in mind, we named this scheme the "Near-Decorrelating Multistage Detector"(NDMD). To demonstrate NDMD performance, we performed two kinds of computer simulations. In the first kind of simulation, simple conditions are assumed in order to evaluate basic cancelling performance. In the other kind of simulation, essential techniques for CDMA cellular systems such as FEC, transmission power control(TPC), and base band filtering were implemented while taking into account NDMD as applied to such systems. These simulations numerically demonstrate that NDMD is very efficient in cancelling out interference and that it improves asynchronous DS-CDMA performance.

Microcellular radio direct-sequence code division multiple access (DC-CDMA) system using optical link to connect their base stations to a central station is a solution of cost-effective and efficient spectrum reuse to meet the growing demand for mobile communications. In addition to the inherent multiuser interference (MUI) of CDMA signals, the system capacity is significantly reduced by a nonlinear distortion (NLD) due to the nonlinearity of optical link. In this paper, a two-stage cancellation technique is introduced into the system to cancel both the MUI and the NLD. It is performed at the receiver of the central station where the random ingredients of all user signals are estimated, and the MUI and the NLD are rebuilt and removed from the received signal. The validity of the cancellation technique is theoretically analyzed and shown by the numerical results. The analytical method and its results are also applicable to other general nonlinear CDMA.

Multipath interconnection networks can support higher bandwidth than those of nonblocking networks by passing multiple packets to the same output simultaneously and these packets are buffered in the output buffer. The delay-throughput performance of the output buffer in multipath networks is closely related to output traffic distribution, packet arrival process at each output link connected to a given output buffer. The output traffic distributions are different according to the various input traffic patterns. Focusing on nonuniform output traffic distributions, this paper develops a new, general analytic model of the output buffer in multipath networks, which enables us to investigate the delay-throughput performance of the output buffer under various input traffic patterns. This paper also introduces Multipath Crossbar network as a representative multipath network which is the base architecture of our analysis. It is shown that the output buffer performances such as packet loss probability and delay improve as nonuniformity of the output traffic distribution becomes larger.

Most of the existing analytical models for multistage ATM switching fabric are not accurate in the presence of a non-uniform traffic at the input of the switch. In this paper, we discuss the issues in modeling a multistage ATM switching fabric, and investigate the effect of independence assumptions in two previous analytical models. A highly accurate 4-state Markov chain model for evaluating the performance of ATM switching fabrics based on multistage switches with 22 finite output-buffered SEs is proposed. The proposed model correctly reflects the correlation of cell movements between two subsequent cycles and states of the buffers of two adjacent stages. By comparing the results obtained from the oroposed model, existing models and simulations, it has been shown that the proposed model is much more accurate than existing models in the presence of a non-uniform traffic in the switch. The results from the existing models are unsatisfactory in the presence of an increased blocking in the switch arising from a non-uniform traffic in the switch. On the contrary, the proposed model is very robust even under severe blocking in the switch.

This paper proposes new algorithms for diagnosing (detection, identification and location) baseline multistage interconnection networks (MIN) as one of the basic units in a massively parallel system. This is accomplished in the presence of single and multiple faults under a new fault model. This model referred to as the geometric fault model, considers defective crossing connections which are located between adjacent stages, internally to the MIN (therefore, a fault corresponds to a physical bridge fault between two connections). It is shown that this type of fault affects the correct geometry of the network, thus requiring a different testing approach than previous methods. Initially, an algorithm which detects the presence of bridge faults (both in the single and multiple fault cases), is presented. For a single bridge fault, the proposed algorithm locates the fault except in an unique pathological case under which it is logically impossible to differentiate between two equivalent locations of the fault (however, the switching element affected by this fault is uniquely located). The proposed algorithm requires log2 N test vectors to diagnose the MIN as fault free (where N is the number of input lines to the MIN). For fully diagnosing a single bridge fault, this algorithm requires at most 2 log2 N tests and terminates when multiple bridge faults are detected. Subsequently, an algorithm which locates all bridge faults is given. The number of required test vectors is O(N). Fault location of each bridge fault is accomplished in terms of the two lines in the bridge and the numbers of the stages between which it occurs. Illustrative examples are given.

Nonuniform traffic can degrade the overall performance of multistage interconnection networks substantially. In this paper, this performance degradation is traced back to blocking effects that are not present under uniform traffic patterns within a network. This blocking phenomenon is not mentioned in the literature and is termed higher order Head-of-Line-blocking (HOLk-blocking) in this paper. Methods to determine the HOL-blocking order of multistage networks in order to classify the networks are presented. The performance of networks under hot-spot traffic as a function of their HOL-blocking characteristics is studied by simulation. It is shown that network bandwidth and packet delay improve under nonuniform traffics with increasing HOL-blocking order of a network.

Multistage Interconnection Networks (MIN) with multiple outlets are networks which can support higher bandwidth than those of nonblocking networks by passing multiple packets to the same destination. Fault recovery mechanisms are proposed for two of such networks (TBSF/PBSF) with the best use of their inherent fault tolerant capability. With these mechanisms, on-the-fly fault recovery is possible for multiple faults on switching elements. For the link fault, the networks are reconfigured after fault diagnosis, and the network is available with some performance degradation. The bandwidth degradation under multiple faults on link/element is analyzed with both theoretical models and simulation. Through the analysis, F-PBSF shows high fault tolerance under high traffic load and low reliability by using 3 or more banyan networks.