In this paper, an efficient method to reduce computational complexity for pedestrian detection is presented. Since trilinear interpolation is not used, the amount of required operations for histogram of oriented gradient (HOG) feature calculation is significantly reduced. By calculating multi-scale HOG features with integral HOG in a two-stage approach, both high detection rate and speed are achieved in the proposed method.

Automated or semi-automated annotation is a practical solution for large-scale corpus construction. However, the special characteristics of Thai language, such as lack of word-boundary and sentence-boundary markers, trigger several issues in automatic corpus annotation. This paper presents a multi-stage annotation framework, containing two stages of chunking and three stages of tagging. The two chunking stages are pattern matching-based named entity (NE) extraction and dictionary-based word segmentation while the three succeeding tagging stages are dictionary-, pattern- and statist09812490981249ical-based tagging. Applying heuristics of ambiguity priority, NE extraction is performed first on an original text using a set of patterns, in the order of pattern ambiguity. Next, the remaining text is segmented into words with a dictionary. The obtained chunks are then tagged with types of named entities or parts-of-speech (PoS) using dictionaries, patterns and statistics. Focusing on the reduction of human intervention in corpus construction, our experimental results show that the dictionary-based tagging process can assign unique tags to 64.92% of the words, with the remaining of 24.14% unknown words and 10.94% ambiguously tagged words. Later, the pattern-based tagging can reduce unknown words to only 13.34% while the statistical-based tagging can solve the ambiguously tagged words to only 3.01%.

This paper presents a fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator (DSM), with an analog error cancellation logic circuit, and a digital decimation filter that is fabricated using 0.18-µm CMOS technology. The 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e2). This error can be eliminated using an analog error cancellation logic circuit. In the proposed differential sample-and-hold circuit, low input impedance is presented with feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror. Also, measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3 dB, 69 dB, 10.9 bits, 12.3 mW, and 0.200.21 mm2, respectively, with a bandwidth of 40 kHz, a sampling rate of 10.24 MHz, an OSR of 128 and a supply voltage of 1.8 V.

A low-complexity method for angle estimation in Multiple-input multiple-output radar (MIMO) radar is presented. In this approach, the signal subspace can be spanned by the orthogonal vectors which are obtained by Multi-stage Wiener Filter (MSWF), then the ESPRIT method can be used to estimate direction of departures (DODs) and direction of arrivals (DOAs). Compared with the conventional ESPRIT algorithm, the proposed method does not involve estimation of the covariance matrix and its eigen-decomposition, which alleviates remarkably the computational complexity. Moreover, the proposed method achieves the similar angle estimation performance. Simulation results are presented to verify the efficiency of the proposed method.

Clock gating is supported by commercial tools as a power optimization feature based on the guard signal described in HDL (structural method). However, the identification of control signals for gated registers is hard and designer-intensive work. Besides, since the clock gating cells also consume power, it is imperative to minimize the number of inserted clock gating cells and their switching activities for power optimization. In this paper, we propose an automatic multi-stage clock gating algorithm with ILP (Integer Linear Programming) formulation, including clock gating control candidate extraction, constraints construction and optimum control signal selection. By multi-stage clock gating, unnecessary clock pulses to clock gating cells can be avoided by other clock gating cells, so that the switching activity of clock gating cells can be reduced. We find that any multi-stage control signals are also single-stage control signals, and any combination of signals can be selected from single-stage candidates. The proposed method can be applied to 3 or more cascaded stages. The multi-stage clock gating optimization problem is formulated as constraints in LP format for the selection of cascaded clock-gating order of multi-stage candidate combinations, and a commercial ILP solver (IBM CPLEX) is applied to obtain the control signals for each register with minimum switching activity. Those signals are used to generate a gate level description with guarded registers from original design, and a commercial synthesis and layout tools are applied to obtain the circuit with multi-stage clock gating. For a set of benchmark circuits and a Low Density Parity Check (LDPC) Decoder (6.6k gates, 212 F.F.s), the proposed method is applied and actual power consumption is estimated using Synopsys NanoSim after layout. On average, 31% actual power reduction has been obtained compared with original designs with structural clock gating, and more than 10% improvement has been achieved for some circuits compared with single-stage optimization method. CPU time for optimum multi-stage control selection is several seconds for up to 25k variables in LP format. By applying the proposed clock gating, area can also be reduced since the multiplexors controlling register inputs are eliminated.

A sensing efficiency optimization scheme based on two-stage spectrum sensing that maximizes the achievable throughput of the secondary network and minimizes the average sensing time is proposed in this paper. A selection method for the threshold is proposed and proved to ensure optimal sensing performance. An effective iterative algorithm is presented to solve the constructed efficiency optimization problem.

In this letter, a two-stage TOA estimation scheme is proposed for positioning in OFDM-based WLAN systems under indoor environments. The estimation scheme consists of coarse estimation and fine estimation. The presented scheme effectively exploits the preamble of the OFDM-based WLAN for accurate estimation. The simulation results exhibit that the performance of the proposed approach is comparable to that of super-resolution estimation even with lower computational complexity.

A spectrum sensing scheme for cognitive radio that includes coarse and fine sensing stages based on cyclostationarity is proposed in this paper. The cyclostationary feature detection (CFD) based on a single cyclic frequency (SCF) is used in the coarse sensing stage and that based on multiple cyclic frequencies (MCF) is employed in the fine sensing stage. Whether the fine sensing stage is performed or not is decided by comparing the statistic constructed in the coarse sensing stage with two thresholds. Theoretical analyses and simulation results show that the proposed sensing scheme has superior sensing performance and needs shorter sensing time.

This paper discusses a dual-stage detection scheme composed of coarse detection stage and refined detection stage for the continuous detection operation of Ultra-Wideband (UWB) detect and avoid (DAA). The threshold factor for the probability of indefinite detection is first proposed and defined to combine the two stages. The proposed scheme focuses on the integration of two different detection schemes with different complexities in order to reduce total computational complexity. A Single-carrier Frequency Division Multiple Access (SC-FDMA) uplink system operating in a Time Division Duplex (TDD) mode is utilized to evaluate the proposed detection scheme. Simulation results indicate that the proposed scheme can make a tradeoff between the detection performance and the computational complexity by setting the probability of indefinite detection.

This paper presents a novel time-domain design procedure for fast-settling three-stage nested-Miller compensated (NMC) amplifiers. In the proposed design methodology, the amplifier is designed to settle within a definite time period with a given settling accuracy by optimizing both the power consumption and silicon die area. Detailed design equations are presented and the circuit level simulation results are provided to verify the usefulness of the proposed design procedure with respect to the previously reported design schemes.

This paper describes a least complex, high speed decoding method named multi-stage threshold decoding (MTD-DR). Each stage of MTD-DR is formed by the traditional threshold decoder with a special shift register, called difference register (DR). After flipping each information bit, DR helps to shorten the Hamming and the Euclidian distance between a received word and the decoded codeword for hard and soft decoding, respectively. However, the MTD-DR with self-orthogonal convolutional codes (SOCCs), type 1 in this paper, makes an unavoidable error group, which depends on the tap connection patterns in the encoder, and limits the error performance. This paper introduces a class of SOCCs type 2 which can breakdown that error group, as a result, MTD-DR gives better error performance. For a shorter code (code length = 4200), hard and soft decoding MTD-DR achieves 4.7 dB and 6.5 dB coding gain over the additive white Gaussian noise (AWGN) channel at the bit error rate (BER) 10-5, respectively. In addition, hard and soft decoding MTD-DR for a longer code (code length = 80000) give 5.3 dB and 7.1 dB coding gain under the same condition, respectively. The hard and the soft decoding MTD-DR experiences error flooring at high Eb/N0 region. For improving overall error performance of MTD-DR, this paper proposes parity check codes concatenation with soft decoding MTD-DR as well.

A low-voltage class-AB CMOS output stage with a tunable quiescent current control circuit is presented. It is based on a complementary common source. The quiescent current is detected by a compact circuit and can be adjusted by means of a control current without need to modify the transistor dimensions. The minimum supply voltage can be down to one threshold voltage plus two saturation voltages. It is suitable to drive low resistive loads. Simulation results are provided that are in agreement with expected characteristics.

In this letter, we propose a novel approach to estimate three different kinds of phone mismatch penalty matrices for two-stage keyword spotting. When the output of a phone recognizer is given, detection of a specific keyword is carried out through text matching with the phone sequences provided by the specified keyword using the proposed phone mismatch penalty matrices. The penalty matrices associated with substitution, insertion and deletion errors are estimated from the training data through deliberate error generation. The proposed approach has shown a significant improvement in a Korean continuous speech recognition task.

H.264/AVC encoder employs rate control to adaptively adjust quantization parameter (QP) to enable coded video to be transmitted over a constant bit-rate (CBR) channel. In this topic, bit allocation is crucial since it is directly related with actual bit generation and the coding quality. Meanwhile, the rate-distortion-optimization (RDO) based mode-decision technique also affects performance a lot for the strong relation among mode, bits, and quality. This paper presents a multi-stage rate control scheme for R-D optimized H.264/AVC encoders under CBR video transmission. To enhance the precision of the complexity estimation and bit allocation, a frequency-domain parameter named mean-absolute-transform-difference (MATD) is adopted to represent frame and macroblock (MB) residual complexity. Second, the MATD ratio is utilized to enhance the accuracy of frame layer bit prediction. Then, by considering the bit usage status of whole sequence, a measurement combining forward and backward bit analysis is proposed to adjust the Lagrange multiplier λMODE on frame layer to optimize the mode decision for all MBs within the current frame. On the next stage, bits are allocated on MB layer by proposed remaining complexity analysis. Computed QP is further adjusted according to predicted MB texture bits. Simulation results show the PSNR improvement is up to 1.13 dB by using our algorithm, and the stress of output buffer control is also largely released compared with the recommended rate control in H.264/AVC reference software JM13.2.

This paper proposes the sleep stage estimation method that can provide an accurate estimation for each person without connecting any devices to human's body. In particular, our method learns the appropriate multiple band-pass filters to extract the specific wave pattern of heartbeat, which is required to estimate the sleep stage. For an accurate estimation, this paper employs Learning Classifier System (LCS) as the data-mining techniques and extends it to estimate the sleep stage. Extensive experiments on five subjects in mixed health confirm the following implications: (1) the proposed method can provide more accurate sleep stage estimation than the conventional method, and (2) the sleep stage estimation calculated by the proposed method is robust regardless of the physical condition of the subject.

Due to the advancement of software radio and RF technology, cognitive radio(CR) has become an enabling technology to realize dynamic spectrum access through its spectrum sensing and reconfiguration capability. Robust and reliable spectrum sensing is a key factor to discover spectrum opportunity. Single cognitive radios often fail to provide such reliable information because of their inherent sensitivity limitation. Primary signals that are subject to detection by cognitive radios may become weak due to several factors such as fading and shadowing. One approach to overcome this problem is to perform spectrum sensing by using multiple CRs or multiple spectrum sensors. This approach is known as distributed sensing because sensing is carried out through cooperation of spatially distributed sensors. In distributed sensing, sensors should perform spectrum sensing and forward the result to a destination where data fusion is carried out. Depending on the channel conditions between sensors (sensor-to-sensor channel) and between the sensor and the radio (user-channel), we explore different spectrum sensing algorithms where sensors provide the sensing information either cooperatively or independently. Moreover we investigate sensing schemes based on soft information combining (SC), hard information combining (HC). Finally we propose a two-stage detection scheme that uses both SC and HC. The newly proposed detection scheme is shown to provide improved performance compared to sensing based on either HC or SC alone. Computer simulation results are provided to illustrate the performances of the different sensing algorithms.

The multiobjective route selection problem (m-RSP) is a key research topic in the car navigation system (CNS) for ITS (Intelligent Transportation System). In this paper, we propose an interactive multistage weight-based Dijkstra genetic algorithm (mwD-GA) to solve it. The purpose of the proposed approach is to create enough Pareto-optimal routes with good distribution for the car driver depending on his/her preference. At the same time, the routes can be recalculated according to the driver's preferences by the multistage framework proposed. In the solution approach proposed, the accurate route searching ability of the Dijkstra algorithm and the exploration ability of the Genetic algorithm (GA) are effectively combined together for solving the m-RSP problems. Solutions provided by the proposed approach are compared with the current research to show the effectiveness and practicability of the solution approach proposed.

This letter proposes a mismatch insensitive switched-capacitor multiply-by-four (4X) amplifier using the voltage addition scheme. The proposed circuit provides 2-times faster speed and about half of silicon area when compared with the cascade of conventional 2X amplifiers. Monte-Carlo simulation results show about 15% gain accuracy improvement over the cascaded 2X- amplifiers.

This paper proposes a low power and high speed track and hold circuit (T/H circuit) based on the two-stage structure. The proposed circuit consists of two internal T/H circuits connected in cascade. The first T/H circuit converts an input signal into a step voltage and it is applied to the following second T/H circuit which drives large load capacitors and consumes large power. Applying the step voltage to the second T/H circuit prevents the second T/H circuit from charging and discharging its load capacitor during an identical track phase and enables low power operation. Thanks to the two-stage structure the proposed T/H circuit can save 29% of the power consumption compared with the conventional one. An optimum design procedure of the proposed two stage T/H circuit is explained and its validity is confirmed by HSPICE simulations.

The multistage Wiener filter (MWF) outperforms the full rank Wiener filter in low sample support environments. However, the MWF adaptive process should be stopped at an optimum stage to get the best performance. There are two methods to stop the MWF adaptive process. One method is to calculate until the final full-stage, and the second method is to terminate at r-stage less than full-stage. The computational load is smaller in the latter method, however, a performance degradation is caused by an additional or subtractive stage calculation. Therefore, it is very important for the r-stage calculation to stop an adaptive process at the optimum stage. In this paper, we propose a simple method based on a cross-correlation coefficient to stop the MWF adaptive process. Because its coefficient is calculated by the MWF forward recursion, the optimum stage is determined automatically and additional calculations are avoided. The performance was evaluated by simulation examples, demonstrating the superiority of the proposed method.