This paper presents the improvement of the transient response and stability for a two-stage DC-DC converter by removing the output inductor. The conventional two-stage converter consists of a buck converter used as the first stage and a half-bridge converter used as the second stage. The proposed circuit topology removing the output inductor and the conventional topology are compared. Removing the output inductor results in the system-order reduction of the transfer function. As a result, the stability is improved, and the crossover frequency of the open-loop transfer function becomes higher. The effectiveness of the proposed circuit topology was experimentally confirmed.

A simple method has been proposed for the measurement of the output power and phase characteristics of the 3rd-order inter-modulation distortion (IM3) components appearing in multistage power amplifiers. By adopting a unique definition of the phase for the IM3 components that is independent of the delay time caused by transmission lines and other instrument devices, it is possible to measure the phase, merely by using a vector signal analyzer. It is demonstrated that an accurate estimation of the IM3 characteristics of two-stage cascaded power amplifiers for cellular radio handheld terminals can be made by using the IM3 characteristics of the 1st and 2nd-stage amplifiers as measured by the proposed method. The results indicate that it is possible to reduce the dissipation power by 18% at 28 dBm RF output power with respect to conventional measurement methods. Further studies show that the error in the resultant vector of the estimated IM3 is less than 1 dB, when the asymmetry characteristics of the IM3 sidebands in the 2nd-stage amplifier are less than 7.3%.

By adding an auxiliary transformer to a single-stage single-switch power-factor-corrected converter (S4PFCC), the storage capacitor voltage and its range of voltage change against line voltage change are reduced. In addition, this transformer provides a direct power transfer path for input line to output load to increase the conversion efficiency. High power factor is maintained due to the elimination of dead angle of the input current. This paper presents detailed analysis and optimal design of a discontinuous conduction mode (DCM) boost-flyback S4PFCC with the auxiliary transformer. Experimental results for a 15 V/60 W prototype and with comparison to a S4PFCC without the auxiliary transformer are given to show the proposed approach effective.

In a content-based image retrieval (CBIR) system, both the retrieval relevance and the response time are very important. This letter presents the condensed two-stage search method as a new fast image retrieval approach by making use of the property of Cauchy-Schwarz inequality. The method successfully reduces the overall processing time for similarity computation, while maintaining the same retrieval relevance as the conventional exhaustive search method. By the extensive computer simulations, we observe that the condensed two-stage search method is more effective as the number of images and dimensions of the feature space increase.

The High-Low Water Mark destage (HLWM) algorithm is widely used to enable cached RAID5 to flush dirty data from its write cache to disks due to the simplicity of its operations. It starts and stops a destaging process based on the two thresholds that are configured at the initialization time with the best knowledge of its underlying storage performance capability and its workload pattern which includes traffic intensity, access patterns, etc. However, each time the current workload varies from the original, the thresholds need to be re-configured with the changed workload. This paper proposes an efficient destage algorithm which automatically re-configures its initial thresholds according to the changed traffic intensity and access patterns, called adaptive thresholding. The core of adaptive thresholding is to define the two thresholds as the multiplication of the referenced increasing and decreasing rates of the write cache occupancy level and the time required to fill and empty the write cache. We implement the proposed algorithm upon an actual RAID system and then verify the ability of the auto-reconfiguration with synthetic workloads having a different level of traffic intensity and access patterns. Performance evaluations under well-known traced workloads reveal that the proposed algorithm reduces disk IO traffic by about 12% with a 6% increase in the overwrite ratio compared with the HLWM algorithm.

In order to increase the capacity of a DS-CDMA system, several kinds of interference suppression techniques have been studied, such as multiple access interference (MAI) cancellers and adaptive array antennas. However, their performance tends to degrade in high traffic-load situations. To compensate for the degradation, a receiver cascading an adaptive array antenna and a multistage parallel interference canceller (PIC) is studied in this paper. This receiver first uses an adaptive array antenna to suppress interference signals spatially, and uses a multistage PIC to suppress in-beam interference effectively. The performance of the cascaded receiver is evaluated with two schemes for antenna weight generation by computer simulations assuming a Rayleigh-distributed L-path channel. When antenna weights are generated for each user by an LMS algorithm, the cascaded receiver has shown better performance at the cost of a large number of pilot symbols and symbol by symbol weight update. Its performance degradation is 2.8 dB at the BER of 10-4 even when the number of users increases from one to 24. On the other hand, when antenna weights are generated for each path by a DMI algorithm, its performance is degraded due to the inaccurate weight generation which occurs when the SINR of the desired signal is small. This degradation can be mitigated by using all signals of the desired user received by all antenna patterns of desired user for RAKE combining when the difference among arrival angles of the paths of the desired user is small.

In this paper, we propose a modified CP-AFC (Cross-Product Automatic Frequency Control) algorithm to enhance coherent signal detection for WCDMA reverse link receiver. We introduce a moving average filter at the FDD input to decrease the noise effect by increasing the number of cross-products, since pilot symbol in WCDMA is not transmitted continuously. We also add normalization algorithm to overcome the conventional CP-FDD's sensitivity to the variance of input signal amplitude and to increase the linear range of S-curve. For rapid frequency acquisition and tracking, we adopt a multi-stage tracking mode. We applied the proposed algorithm in the implementation of WCDMA base station modem successfully.

We introduce a PLL (Phase Locked Loop) for low-power and a low supply voltage applications. Because the PLL is a key device of the system LSIs used in mobile terminals, it is very important that PLLs operate under a low supply voltage to reduce power consumption. We investigate the limitations of the conventional VCO that we proposed in Ref.[5] and propose a modified VCO that uses common load transistors. Furthermore, we propose a charge pump that uses a dynamic output stage op-amp and a stability technique for the CMOS process, and it does not contain any special resistors. The results of an evaluation of a device fabricated using a standard logic 0.18-µm CMOS process demonstrated that the proposed PLL operated above 1.0 GHz with a 1.2-V supply voltage and it produced only a small amount of jitter that was lower than 78 psp-p.

MOSFETs can be used as capacitors, but its capacitance can vary by 5 to 7 times as its terminal voltage varies. To reduce the voltage dependence of the capacitance, this paper proposed two types of devices: one is called accumulation MOSFET (AMOS) and the other is formed by two conventional PMOS connected in anti-parallel. These two devices are readily available in the standard digital CMOS processes. The proposed capacitors were implemented in three different CMOS processes. The measured results show that the capacitances of both devices have less voltage dependence than a single PMOS. The voltage dependence of the AMOS capacitance can be as small as 17%. The minimum capacitance per unit area of the AMOS is 1.8 times that of the double-poly capacitor in an analog/mixed-mode CMOS process. To verify the usefulness of these two types of capacitors, they are used as compensation capacitors in a conventional two-stage amplifier. The measured results show that the amplifier compensated by the AMOS capacitor has little variation (6%) of the unity-gain frequency over the input common-mode range. Due to its smaller die area and cheaper digital process, AMOS can be used as compensation capacitor without resorting to more expensive analog process.

For several years, more and more people are joining the Internet and various kind of packets (so called transaction-, block-, and stream-types) have been transmitted in the same network, so that poor network conditions cause loss of the stream-type data packets, such as voices, which request smaller transmission delay time than others. We consider a switching node (router) in a network as an N-series M/G/1-type queueing model and have mainly evaluated the fluctuation of packet delay time and end-to-end delay time, using the two moments matching method with initial value, then define the delay jitter D of a network which consists of jointed N switching nodes. It is clarified that this network is not suitable for voice packets transmission media without measures.

This paper investigates the interference suppression effect from much higher rate dedicated physical channels (DPCHs) of a parallel-type coherent multistage interference canceller (COMSIC) with iterative channel estimation (ICE) by laboratory experiments in the transmit-power-controlled W-CDMA reverse link. The experimental results elucidate that when two interfering DPCHs exist with the spreading factor (SF) of 8 and with the ratio of the target signal energy per bit-to-interference power spectrum density ratio (Eb/I0) of fast transmit power control, ΔEb/I0, of -6 dB (which corresponds to 64 simultaneous DPCHs with SF = 64, i.e., the same symbol rate as the desired DPCH), the implemented COMSIC receiver with ICE exhibits a significant decrease in the required transmit signal energy per bit-to-background noise power spectrum density ratio (Eb/N0) at the average bit error rate (BER) of 10-3 (while the matched filter (MF)-based Rake receiver could not realize the average BER of 10-3 due to severe multiple access interference (MAI)). It is also found that the achieved BER performance at the average BER of 10-3 of the COMSIC receiver with the A/D converter quantization of 8 bits in the laboratory experiments is degraded by approximately 1.0 dB and 4.0 dB compared to the computer simulation results, when ΔEb/I0=-6 dB and -9 dB, respectively, due to the quantization error of the desired signal and path search error for the Rake combiner. Finally, we show that the required transmit Eb/N0 at the average BER of 10-3 of the third-stage COMSIC with ICE is decreased by approximately 0.3 and 0.5 dB compared to that of COMSIC with decision-feedback type channel estimation (DFCE) with and without antenna diversity reception, respectively.

In this paper we propose a MIN (Multistage Interconnection Network) whose performance in the faulty case degrades as gracefully as possible. We focus on a two-dilated baseline network as a sort of MIN. The link connection pattern in our MIN is determined so that all the available paths established between an input terminal and an output terminal via an identical input of a SE (Switching Element) in some stage will never pass through an identical SE in the next stage. Extra links are useful in improving the performance of the MIN and do not complicate the routing scheme. There is no difference between our MIN and others constructed from a baseline network with regard to numbers of links and cross points in all SEs. The theoretical computation and simulation-based study show that our MIN is superior to others in performance, especially in robustness against concentrated SE faults in an identical stage.

A novel multilevel construction for permutation codes is presented. A permutation code of length n is a subset of all the vectors obtained from coordinate permutations on the vector (0,1,. . . ,n-1). We would like to construct a permutation code with cardinality as large as possible for a given code length n and a minimum distance. The proposed construction is available when n = 2m (m is a positive integer). We exploit m-constant weight binary codes as component codes and combine them in a multilevel way. Permutation codes with various parameters can be constructed by selecting appropriate combination of component codes. Furthermore, multi-stage decoding is available for decoding the permutation codes constructed by the proposed construction.

Reliability-based decoding algorithm in multistage decoding of multilevel codes is discussed. Through theoretical analyses, effects of soft reliability information are examined for different types of partitionings.

This paper deals with the approximation of multi-dimensional chaotic dynamics by using the multi-stage fuzzy inference system. The number of rules included in multi-stage fuzzy inference systems is remarkably smaller compared to conventional fuzzy inference systems where the number of rules are proportional to an exponential of the number of input variables. We also propose a method to optimize the shape of membership function and the appropriate selection of input variables based upon the genetic algorithm (GA). The method is applied to the approximation of typical multi-dimensional chaotic dynamics. By dividing the inference system into multiple stages, the total number of rules is sufficiently depressed compared to the single stage system. In each stage of inference only a portion of input variables are used as the input, and output of the stage is treated as an input to the next stage. To give better performance, the shape of the membership function of the inference rules is optimized by using the GA. Each individual corresponds to an inference system, and its fitness is defined by using the prediction error. Experimental results lead us to a relevant selection of the number of input variables and the number of stages by considering the computational cost and the requirement. Besides the GA in the optimization of membership function, we use the GA to determine the input variables and the number of input. The selection of input variable to each stage, and the number of stages are also discussed. The simulation study for multi-dimensional chaotic dynamics shows that the inference system gives better prediction compared to the prediction by the neural network.

In SDMA, a spatial domain interference canceller applying a multistage processing concept to the MMSE multibeam adaptive array has an attractive feature. Weak power signals strongly interfered can be detected in the succeeded stages after removing other strong power signals which are already detected. This idea can be enhanced to the reference timing estimation required in the MMSE algorithm. In this paper, the spatial domain interference canceller introducing multistage timing estimation is proposed and its performance is evaluated by computer simulations. The results show that the timing estimation performance highly improved.

A large-signal simulation program for multi-stage power amplifier modules by using a novel interpolation is presented. This simulation program has the function to make the Load-Pull and Source-Pull (LP/SP) data required for the simulation. By using the interpolation, a lot of LP/SP data can be made from a small number of measured LP/SP data. The interpolation is based on the calculation method using a two-dimensional function. By using the simulation program, we can calculate the large-signal characteristics depended on frequency and temperature of the multi-stage amplifier module. We apply the simulation program to the design of the amplifier. The calculated and measured results agree well. The accuracy of the presented interpolation is confirmed. It is considered that the presented program is useful to calculate large-signal characteristics of the amplifier module.

The stage 3/2 decoding scheme, originally suggested by U. Timor, is modified for a Rayleigh fading channel to improve the performance of a fast frequency-hopped multiple access/multilevel frequency shift keying system. When signal-to-noise ratio per bit is 30 dB, the simulation results show that the modified stage 3/2 decoding scheme increases the spectral efficiency by 11% compared to the modified stage 1 decoding scheme at bit error rate of 10-3. Further, the performance comparisons are made between the modified multistage decoding scheme and the diversity combining methods, where the modified stage 3/2 decoding scheme shows better performance.

In order to increase the link capacity in the wideband direct sequence code division multiple access (W-CDMA) reverse link, employing a parallel-type coherent multi-stage interference canceller (COMSIC) is more practical than employing a serial (successive)-type due to its inherent advantage of a short processing delay, although its interference suppression effect is inferior to that of the serial-type. Therefore, this paper proposes a parallel-type COMSIC with iterative channel estimation (ICE) using both pilot and decision-feedback data symbols at each canceling stage in order to improve the interference suppression effect of the parallel-type COMSIC. Computer simulation results demonstrate that by applying the parallel-type COMSIC with ICE after FEC decoding, the capacity in an isolated cell can be increased by approximately 1.6 (2.5) times that of the conventional parallel-type COMSIC with channel estimation using only pilot symbols (the MF-based Rake receiver) at the required average transmit Eb/N0 of 15 dB, i.e. in the interference-limited channel. The results also show that, although the capacity in the isolated cell with the parallel-type COMSIC with ICE after FEC decoding is degraded by approximately 6% compared to that with the serial-type COMSIC with ICE after FEC decoding, the processing delay can be significantly decreased owing to the simultaneous parallel operation especially when the number of active users is large.

It is difficult for an adaptive array to reduce interference signals efficiently from received signals when the interference signals and desired signal are closely located. This is a problem for a spatial division multiple access (SDMA) system using the multibeam adaptive array as a multiuser detector. In this paper, we propose a space domain multistage interference canceller (SD-MIC) for the SDMA system. Its performance is evaluated by computer simulations, assuming Japanese personal handy phone system (PHS) uplink environments. The results show remarkable improvement in high spatial correlation situations.