When the joint source-channel (JSC) decoder is used for source coding over noisy channels, the JSC decoder may invent errors even though the received data is not corrupted by the channel noise, if the JSC decoder assumes the channel was noisy. A novel encoder algorithm has been recently proposed to improve the performance of the communications system under this situation. In this letter, we propose another algorithm based on conditional entropy-constrained vector quantizer to further improve the encoder. The algorithm proposed in this letter significantly improves the performance of the communications system when the hypothesized channel bit error rate is high.

In spectrum-sharing systems where the secondary user (SU) opportunistically accesses the primary user (PU)'s licensed channel, the SU should satisfy both the transmit power constraint of the SU transmitter and the received power constraint at the PU receiver. This letter studies the ergodic capacity of spectrum-sharing systems in fading channels. The ergodic capacity expression along with the optimal power allocation scheme is derived considering both the average transmit and received power constraints. The capacity function in terms of the two power constraints is found to be divided into transmit power limited region, received power limited region and dual limited region. Numerical results in Rayleigh fading channels are presented to verify our analysis.

This paper presents a deadbeat control scheme for linear systems with state constraints. The proposed controller increases the number of steps on-line for the deadbeat tracking performance, satisfying given admissible state constraints. LMI conditions are given to minimize the unavoidable step delay. The proposed schemes can be easily developed by using LMI approach, and are validated by numerical simulation.

For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. This paper treats the hold constraint in a datapath circuit, and discusses a register assignment in high level synthesis considering delay variations. Our approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). One of our contributions is to show that the minimization of the number of minimum-path delay compensated FUs is NP-hard in general, and it is in the class P if the number of FUs is a constant. A polynomial time algorithm for the latter is also shown in this paper. In addition, an integer linear programming (ILP) formulation is also presented. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.

In this paper, we propose a set of constraints for adaptive broad-band beamforming in the presence of angular errors. We first present spatial and frequency derivative constraints (SFDC) for the design of the quiescent beamformer response. With the wavelet-based blocking matrices, the proposed generalized sidelobe canceller (GSC) preserves the desired signal, and it is less sensitive to the broad-band noise. To make this beamformer more robust to the directional mismatch, we add a pseudo-interference algorithm in the weight adaptive process. Analysis and simulation results demonstrate that the angular beamwidth is insensitive to the input signal-to-noise ratio (SNR).

Symmetry constrains are the constraints that the given cells should be placed symmetrically in design of analog ICs. We use O-tree to represent placements and propose a decoding algorithm which can obtain one of the minimum placements satisfying the constraints. The decoding algorithm uses linear programming, which is too much time consuming. Therefore we propose a graph based method to recognize if there exists no placement satisfying both the given symmetry and O-tree constraints, and use the method before application of linear programming. The effectiveness of the proposed method was shown by computational experiments.

In equational theorem proving, convergent term rewriting systems play a crucial role. In order to compute convergent term rewriting systems, the standard completion procedure (KB) was proposed by Knuth and Bendix and has been improved in various ways. The multi-completion system MKB developed by Kurihara and Kondo accepts as input a set of reduction orders in addition to equations and efficiently simulates parallel processes each of which executes the KB procedure with one of the given orderings. Wehrman and Stump also developed a new variant of completion procedure, constraint-based completion, in which reduction orders need not be given by using automated modern termination checkers. As a result, the constraint-based procedures simulate the execution of parallel KB processes in a sequential way, but naive search algorithms sometimes cause serious inefficiency when the number of the potential reduction orders is large. In this paper, we present a new procedure, called a constraint-based multi-completion procedure MKBcs, by augmenting the constraint-based completion with the framework of the multi-completion for suppressing the combinatorial explosion by sharing inferences among the processes. The existing constraint-based system SLOTHROP, which basically employs the best-first search, is more efficient when its built-in heuristics for process selection are appropriate, but when they are not, our system is more efficient. Therefore, both systems have their role to play.

Automated static timing analysis methods provide a safe but usually overestimated worst-case execution time (WCET) due to infeasible execution paths. In this paper, we propose a visual language, User Constraint Language (UCL), to obtain a tight WCET estimation. UCL provides intuitive visual notations with which users can easily specify various levels of flow information to characterize valid execution paths of a program. The user constraints specified in UCL are translated into finite automata. The combined automaton, constructed by a cross-production of the automata for program and user constraints, reflects the static structure and possible dynamic behavior of the program. It contains only the execution paths satisfying user constraints. A case study using part of a software program for satellite flight demonstrates the effectiveness of UCL and our approach.

A novel algorithm for source location by utilizing the time-difference-of-arrival (TDOA) of a signal received at spatially separated sensors is proposed. The algorithm is based on the constrained total least-squares (CTLS) technique and gives an explicit solution. Simulation results demonstrate that the proposed algorithm has high location accuracy and its performance is close to the Cramer-Rao lower bound (CRLB).

In multi-FPGA prototyping systems for circuit verification, serialized time-multiplexed I/O technique is used because of the limited number of I/O pins of an FPGA. The verification time depends on a selection of inter-FPGA signals to be time-multiplexed. In this paper, we propose a method that minimizes the verification time of multi-FPGA systems by finding an optimal selection of inter-FPGA signals to be time-multiplexed. In the experiments, it is shown that the estimated verification time is improved 38.2% on average compared with conventional methods.

Recently, multi-car elevator (MCE) system has captured attention as an effective mean for the improvement of transportation capability in a high-rise building. The MCE has two or more cars in one shaft. In this paper, we propose an algorithm for group controllers of MCE system, and show the effectiveness of our algorithm through computer simulation.

A total-field/scattered-field (TF/SF) boundary which is commonly used in the finite-difference time-domain (FDTD) method to illuminate scatterers by plane waves, is developed for use in the constrained interpolation profile (CIP) method. By taking the numerical dispersion into account, the nearly perfect TF/SF boundary can be achieved, which allows us to calculate incident fields containing high frequency components without fictitious scattered fields. First of all, we formulate the TF/SF boundary in the CIP scheme. The numerical dispersion relation is then reviewed. Finally the numerical dispersion is implemented in the TF/SF boundary to estimate deformed incident fields. The performance of the nearly perfect TF/SF boundary is examined by measuring leaked fields in the SF region, and the proposed method drastically diminish the leakage compared with the simple TF/SF boundary.

Rapid advances in semiconductor manufacturing technology have led to higher chip power densities, which places greater emphasis on packaging and temperature control during testing. For system-on-chips, peak power-based scheduling algorithms have been used to optimize tests under specified power constraints. However, imposing power constraints does not always solve the problem of overheating due to the non-uniform distribution of power across the chip. This paper presents a TAM/Wrapper co-design methodology for system-on-chips that ensures thermal safety while still optimizing the test schedule. The method combines a simplified thermal-cost model with a traditional bin-packing algorithm to minimize test time while satisfying temperature constraints. Furthermore, for temperature checking, thermal simulation is done using cycle-accurate power profiles for more realistic results. Experiments show that even a minimal sacrifice in test time can yield a considerable decrease in test temperature as well as the possibility of further lowering temperatures beyond those achieved using traditional power-based test scheduling.

As one of the technologies for the retrieval of desired contents over large-scale networks, multi-agent systems are receiving much attention. Since there are too many contents on the network to search them all exhaustively, some applications on multi-agent systems have time constraints, that is, they must obtain a result by a given deadline. To find better results for such applications, it is important for the agents to complete their tasks on as many nodes as possible by the deadline. However, most existing agent systems using round robin scheduling disciplines do not take time constraints into account. Therefore, agents are likely to miss their deadlines on many nodes. In this paper, we propose an efficient agent-dispatching method for time-constrained applications. This method decides creation and migration of a clone agent according to the estimated value of the number of agents that would have completed their tasks by the deadline. The results of our performance evaluation show that the proposed method increases the number of agents that complete their tasks.

Sensor networks that carry heterogeneous traffics and are responsible for reporting very time-critical important events necessitate an efficient and robust data dissemination framework. Designing such a framework, that can achieve both the reliability and delay guarantee while preserving the energy efficiency, namely multi-constrained QoS (MCQoS), is a challenging problem. Although there have been many research works on QoS routing for sensor networks, to the best of our knowledge, no one addresses the above three service parameters all together. In this paper, we propose a new aggregate routing model and a distributed aggregate routing algorithm (DARA) that implements the model for achieving MCQoS. DARA is designed for multi-sink, multipath and location aware network architecture. We develop probabilistic models for multipath reliability constraint, sojourn time of a packet at an intermediary node and node energy consumption. Delay-differentiated multi-speed packet forwarding and in-node packet scheduling mechanisms are also incorporated with DARA. The results of the simulations demonstrate that DARA effectively improves the reliability, delay guarantee and energy efficiency.

A dynamic routing and wavelength assignment (RWA) algorithm encompassing physical impairment due to Four-Wave Mixing (FWM) is proposed, assuming conventional On-Off-Keying (OOK) modulation format. The FWM effect is one of the most severe physical impairments to be considered for the future photonic networks since the accumulation of FWM crosstalk causes a fatal degradation in the wavelength-routed optical network performance. A novel cost function is introduced based upon an impairment-constraint-based routing (ICBR) approach, taking into account the network utilization resources and the physical impairment due to FWM crosstalk. Simulations results show that the proposed algorithm leads to a more realistic system performance compared to those of related approaches of dynamic RWA that fail to consider physical impairments into the routing scheme.

Three-dimensional visualization using jigsaw-puzzle-like glyphs, or shapes, is proposed as a means of representing grammatical constraints in programming. The proposed visualization uses 3D glyphs such as convex, concave, and wireframe shapes. A semantic constraint, such as a type constraint in an assignment, is represented by an inclusive match between 3D glyphs. An application of the proposed visualization method to a subset of the Java programming language is demonstrated. An experimental evaluation showed that the 3D glyphs are easier to learn and enable users to more quickly understand their relationships than 2D glyphs and 1D symbol sequences.

In this letter we propose a simple adaptive algorithm which solves the unit-norm constrained optimization problem. Instead of conventional parameter norm based normalization, the proposed algorithm incorporates single parameter normalization which is computationally much simpler. The simulation results illustrate that the proposed algorithm performs as good as conventional ones while being computationally simpler.

As the feature size of VLSI becomes smaller, delay variations become a serious problem in VLSI. In this paper, we propose a novel class of robustness for a datapath against delay variations, which is named structural robustness against delay variation (SRV), and propose sufficient conditions for a datapath to have SRV. A resultant circuit designed under these conditions has a larger timing margin to delay variations than previous designs without sacrificing effective computation time. In addition, under any degree of delay variations, we can always find an available clock frequency for a datapath having SRV property to operate correctly, which could be a preferable characteristic in IP-based design.

A floorplan is a subdivision of a rectangle into rectangular faces with horizontal and vertical line segments. We call a floorplan room-to-room when adjacencies between rooms are considered. Fujimaki and Takahashi showed that any room-to-room floorplan can be represented as a permutation. In this paper, we give an O(n)-time algorithm that constructs the vertical and the horizontal constraint graphs of a floorplan for a given permutation under this representation.