In this paper, a balance operation Transimpedance Amplifier (TIA) with low-noise has been implemented for optical receivers in 130 nm SiGe BiCMOS Technology, in which the optimal tradeoff emitter current density and the location of high-frequency noise corner were analyzed for acquiring low-noise performance. The Auto-Zero Feedback Loop (AZFL) without introducing unnecessary noises at input of the TIA, the tail current sink with high symmetries and the balance operation TIA with the shared output of Operational Amplifier (OpAmp) in AZFL were designed to keep balanced operation for the TIA. Moreover, cascode and shunt-feedback were also employed to expanding bandwidth and decreasing input referred noise. Besides, the formula for calculating high-frequency noise corner in Heterojunction Bipolar Transistor (HBT) TIA with shunt-feedback was derived. The electrical measurement was performed to validate the notions described in this work, appearing 9.6 pA/√Hz of input referred noise current Power Spectral Density (PSD), balance operation (VIN1=896mV, VIN2=896mV, VOUT1=1.978V, VOUT2=1.979V), bandwidth of 32GHz, overall transimpedance gain of 68.6dBΩ, a total 117mW power consumption and chip area of 484µm × 486µm.

This paper presents a design of CMOS transimpedance amplifier (TIA) and peaking inductor for high speed, low power and small area. To realize high density integration of optical I/O, area reduction is an important figure as well as bandwidth, power and so on. To determine design parameters of multi-stage inverter-type TIA (INV-TIA) with peaking inductors, we derive a simplified model of the bandwidth and the energy per bit. Multi-layered on-chip inductors are designed for area-effective inductive peaking. A 5-stage INV-TIA with 3 peaking inductors is fabricated in a 65-nm CMOS. By using multi-layered inductors, 0.02 mm2 area is achieved. Measurement results show 45 Gb/s operation with 49 dBΩ transimpedance gain and 4.4 mW power consumption. The TIA achieves 98 fJ/bit energy efficiency.

We present a novel burst-mode transimpedance amplifier (TIA) with a gain-mode switching. The proposed TIA utilizes a regulated-cascode (RGC) input stage for broadband characteristics. To expand a dynamic range, the RGC controls a linear operating range depending on transimpedance gains by adjusting bias conditions. This TIA is implemented using the 0.18μm-CMOS technology. The experimental results show that the proposed TIA IC has a good eye-opening and can respond quickly to the burst data.

This paper presents a 44 Gbit/s Transimpedance Amplifier (TIA) with wide-dynamic range and high-linearity for optical receiver fabricated in 130 nm BiCMOS technology. The TIA has the features of 67dBΩ overall transimpedance gain, a bandwidth of 28GHz, 10pA/√Hz of Input Referred Noise Current Power Spectral Density (IRNCPSD), and a power consumption of 95mW from a 2.5V supply. The Total Harmonic Distortion (THD) is less than 5% for a differential input current up to 2.63mApp, when the static input current is 0.1mA.

A design scheme for a high-speed differential-input limiting transimpedance amplifier (TIA) was developed. The output-stage amplifier of the TIA is investigated in detail in order to suppress undershoot and ringing in the output waveform. The amplifier also includes a peak detector for the received signal strength indicator (RSSI) output, which is used to control the optical demodulator for differential-phase-shift-keying or differential-quadrature-phase-shift-keying formats. The limiting TIA was fabricated on the basis of 1-µm emitter-width InP-based heterojunction-bipolar-transistor (HBT) IC technology. Its differential gain is 39 dB, its 3-dB bandwidth is 27 GHz, and its estimated differential transimpedance gain is 73 dBΩ. The obtained output waveform shows that the developed design scheme is effective for suppressing undershoot and ringing.

This paper is a report on a high ESD breakdown-voltage InP HBT transimpedance amplifier IC for optical video distribution systems. To make ESD breakdown-voltage higher, we designed ESD protection circuits integrated in the TIA IC using base-collector/base-emitter diodes of InP HBTs and resistors. These components for ESD protection circuits have already existed in the employed InP HBT IC process, so no process modifications were needed. Furthermore, to meet requirements for use in optical video distribution systems, we studied circuit design techniques to obtain a good input-output linearity and a low-noise characteristic. Fabricated InP HBT TIA IC exhibited high human-body-model ESD breakdown voltages (±1000 V for power supply terminals, ±200 V for high-speed input/output terminals), good input-output linearity (less than 2.9-% duty-cycle-distortion), and low noise characteristic (10.7 pA/ averaged input-referred noise current density) with a -3-dB-down higher frequency of 6.9 GHz. To the best of our knowledge, this paper is the first literature describing InP ICs with high ESD-breakdown voltages.

An inductive buffer peaking technique is proposed and demonstrated to extend the bandwidth of a 10-Gbit/s transimpedance amplifier (TIA) for optical communications. A TIA using this peaking technique is fabricated based on InGaP/GaAs HBT technology. The advantage of the proposed technique is verified by comparisons based on simulations and experiments. For these comparisons, three different types of TIAs using a basic gain stage, a shunt peaking gain stage and the proposed gain stage, respectively, are fabricated and measured. The measured performance of the proposed TIA shows that this bandwidth extension technique using inductive buffer peaking can be applied to circuit designs which demand wideband frequency response with low power consumption.

This article presents the CMOS transimpedance amplifier (TIA) for gigabits optical communication, where an analytical method for designing a wideband TIA using different inductive peaking technology is introduced. In this study, we derive and analyze the transfer function (Vout/Iin) of the TIA circuit from the equivalent circuit model. By adding the peaking inductor in different locations, the TIA 3-dB bandwidth can be enhanced without sacrificing the transimpedance gain. These TIA designs have been realized by the advanced CMOS process, and the measured results confirm the predictions from the analytic approach, where the inductive peaking is an useful way to enhance the TIA bandwidth.