As we scale toward nanometer technologies, the increase in interconnect parameter variations will bring significant performance variability. New design methodologies will emerge to facilitate construction of reliable systems from unreliable nanometer scale components. Such methodologies require new performance models which accurately capture the manufacturing realities. In this paper, we present a Linear Fractional Transform (LFT) based model for interconnect parametric uncertainty. The new model formulates the interconnect parametric uncertainty as a repeated scalar uncertainty structure. With the help of generalized Balanced Truncation Realization (BTR) and Linear Matrix Inequalities (LMI's), the porposed model reduces the order of the original interconnect network while preserves the stability. The LFT based new model even guarantees passivity if the BTR reduction is based on solutions to a pair of Linear Matrix Inequalities (LMI's) generated from Lur'e equations. In case of large number of uncertain parameters, the new model may be applied successively: the uncertain parameters are partitioned into groups, and with regard to each group, LFT based model is applied in turns.

Multi-cycle Test looks promising a way to reduce the test application time of POST (Power-on Self-Test) for achieving a targeted high fault coverage specified by ISO26262 for testing automotive devices. In this paper, we first analyze the mechanism of Stuck-at Fault Detection Degradation problem in multi-cycle test. Based on the result of our analysis we propose a novel solution named FF-Control Point Insertion technique (FF-CPI) to achieve the reduction of scan-in patterns by multi-cycle test. The FF-CPI technique modifies the captured values of scan Flip-Flops (FFs) during capture operation by directly reversing the value of partial FFs or loading random vectors. The FF-CPI technique enhances the number of detectable stuck-at faults under the capture patterns. The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of FF-CPI technique in scan-in pattern reduction for POST.

In this letter, the interference cancellation technique is introduced to single carrier (SC) block transmission systems in sparse Rician frequency selective fading channels, and an effective equalizer is presented. Hard decision on the transmitted signal is made by commonly used SC equalizers, and every multipath signal can be constructed by the initial solution and channel state information. Then, final demodulation result is obtained by the line-of-sight component in the received signal which can be achieved by cancelling the other multipath signals in the received signal. The solution can be further used to construct the multipath signals allowing a multistage detector with higher performance to be realized. It is shown by Monte Carlo simulations in an SUI-5 channel that the new scheme offers dramatically higher performance than traditional equalization schemes.

A space-time and multipath diversity combining algorithm is presented for STBC single carrier block transmission system with two transmit and one receive antennas. The initial solution is achieved by an STBC-based frequency domain equalizer, and the multipath components in the received signal are decoupled by this initial solution and channel state information. Finally, STBC combining is carried out on each decoupled multipath component separately, and then the single carrier output branches are combined further using the maximal ratio combining (MRC) algorithm.

Cooperative communication provides a new way of introducing spatial diversity to wireless systems. In order to increase the spectral efficiency of coded cooperative relaying system, the adaptive modulation technique is presented under Rayleigh fading channel in this paper. The source and relay adapt their modulation schemes based on the channel condition of all three links, i.e. source to relay, source to destination and relay to destination. Furthermore, since the available channel knowledge of the source to relay link is usually non-ideal at the destination in practice, a simplified estimation of this link quality is also given. Simulation demonstrates the effectiveness of the proposed technique in improving the data throughput.

A new cell structure Power MOSFET, which exhibits a lower on-state resistance and lower gate charge than the conventional layout geometry, is proposed in this research. Vertical Power MOSFETs are generally designed by either squared (closed) cell or stripe (linear) cell geometry; each has its own advantages and drawbacks. Typically, closed cell design has lower on resistance but higher gate charge characteristics than the linear one. In this study, we propose, fabricate, and analyze a "wing cell" structure Power MOSFET, which can have lower on resistance and lower gate charge performances than the closed cell structure. In addition, the wing cell design can avoid the "closed concept" patents.

This paper investigates the transmission capacity of open-loop spatial multiplexing with zero-forcing receivers in overlaid ad hoc networks. We first derive asymptotic closed-form expressions for the transmission capacity of two coexisting networks (a primary network vs. a secondary network). We then address a special case with equal numbers of transmit and receive antennas through exact analysis. Numerical results validate the accuracy of our expressions. Our findings show that the overall transmission capacity of coexisting networks will improve significantly over that of a single network if the primary network can tolerate a slight outage probability increase. This improvement can be further boosted if more streams are configured in the spatial multiplexing scheme; less improvement is achieved by placing more antennas at the receive side than the transmit side. However, when the stream number exceeds a certain limit, spatial multiplexing will produce negative effect for the overlaid network.

In this paper we propose a novel method to reduce power consumption during scan testing caused by test responses at scan-out operation for logic BIST. The proposed method overwrites some flip-flops (FFs) values before starting scan-shift so as to reduce the switching activity at scan-out operation. In order to relax the fault coverage loss caused by filling new FF values before observing the capture values at the FFs, the method employs multi-cycle scan test with partial observation. For deriving larger scan-out power reduction with less fault coverage loss and preventing hardware overhead increase, the FFs to be filled are selected in a predetermined ratio. For overwriting values, we prepare three value filling methods so as to achieve larger scan-out power reduction. Experiment for ITC99 benchmark circuits shows the effectiveness of the methods. Nearly 51% reduction of scan-out power and 57% reduction of peak scan-out power are achieved with little fault coverage loss for 20% FFs selection, while hardware overhead is little that only 0.05%.

In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method.

Due to the dynamics of topology and resources, Call Admission Control (CAC) plays a significant role for increasing resource utilization ratio and guaranteeing users' QoS requirements in wireless/mobile networks. In this paper, a dynamic multi-threshold CAC scheme is proposed to serve multi-class service in a wireless/mobile network. The thresholds are renewed at the beginning of each time interval to react to the changing mobility rate and network load. To find suitable thresholds, a reward-penalty model is designed, which provides different priorities between different service classes and call types through different reward/penalty policies according to network load and average call arrival rate. To speed up the running time of CAC, an Optimized Genetic Algorithm (OGA) is presented, whose components such as encoding, population initialization, fitness function and mutation etc., are all optimized in terms of the traits of the CAC problem. The simulation demonstrates that the proposed CAC scheme outperforms the similar schemes, which means the optimization is realized. Finally, the simulation shows the efficiency of OGA.

Web person search often return web pages related to several distinct namesakes. This paper proposes a new web page model for template-free person data extraction, and uses Dirichlet Process Mixture model to solve name disambiguation. The results show that our method works best on web pages with complex structure.

Memory-based Programmable Logic Device (MPLD) is a new type of reconfigurable device constructed using a general SRAM array in a unique interconnect configuration. This research aims to propose approaches to guarantee the long-term reliability of MPLDs, including a test method to identify interconnect defects in the SRAM array during the production phase and a delay monitoring technique to detect aging-caused failures. The proposed test method configures pre-generated test configuration data into SRAMs to create fault propagation paths, applies an external walking-zero/one vector to excite faults, and identifies faults at the external output ports. The proposed delay monitoring method configures a novel ring oscillator logic design into MPLD to measure delay variations when the device is in practical use. The logic simulation results with fault injection confirm the effectiveness of the proposed methods.

Vertical Power MOSFETs are widely designed by deep well structures for breakdown requirement. In this study, we proposed, simulated, and analyzed a "shallow dual well" structure Power MOSFET, which utilize an n-well to cover the conventional p-well. The cell pitch can be reduced and results in an increased cell density. The reduced cell pitch and increased cell density improves the gate charge and on resistance performances about 66.5% and 15.8% without sacrificing the device breakdown owing to a shallow junction design. In addition, with the dual well structure design, the breakdown point will occur at the center of the well. Therefore, the capability of avalanche energy can be improved about 1.9 times than the tradition well structure.

In this paper, we investigate how to achieve call admission control (CAC) for guaranteeing call dropping probability QoS which is caused by handoff timeout in cognitive radio (CR) networks. When primary user (PU) appears, spectrum handoff should be initiated to maintain secondary user (SU)'s link. We propose a novel virtual queuing (VQ) scheme to schedule spectrum handoff requests sent by multiple SUs. Unlike the conventional first-come-first-served (FCFS) scheduling, resuming transmission in the original channel has higher priority than switching to another channel. It costs less because it avoids the cost of signaling frequent spectrum switches. We characterize the handoff delay on the effect of PU's behavior and the number of SUs in CR networks. And user capacity under certain QoS requirement is derived as a guideline for CAC. The analytical results show that call dropping performance can be greatly improved by CAC when a large amount of SUs arrives fast as well as the VQ scheme is verified to reduce handoff cost compared to existing methods.