Particle swarm optimization (PSO) is a swarm intelligence algorithm and has good search performance and simplicity in implementation. Because of its properties, PSO has been applied to various optimization problems. However, the search performance of the classical PSO (CPSO) depends on reference frame of solution spaces for each objective function. CPSO is an invariant algorithm through translation and scale changes to reference frame of solution spaces but is a rotationally variant algorithm. As such, the search performance of CPSO is worse in solving rotated problems than in solving non-rotated problems. In the reference frame invariance, the search performance of an optimization algorithm is independent on rotation, translation, or scale changes to reference frame of solution spaces, which is a property of preferred optimization algorithms. In our previous study, piecewise-linear particle swarm optimizer (PPSO) has been proposed, which is effective in solving rotated problems. Because PPSO particles can move in solution spaces freely without depending on the coordinate systems, PPSO algorithm may have rotational invariance. However, theoretical analysis of reference frame invariance of PPSO has not been done. In addition, although behavior of each particle depends on PPSO parameters, good parameter conditions in solving various optimization problems have not been sufficiently clarified. In this paper, we analyze the reference frame invariance of PPSO theoretically, and investigated whether or not PPSO is invariant under reference frame alteration. We clarify that control parameters of PPSO which affect movement of each particle and performance of PPSO through numerical simulations.

Approximate computing has emerged as a promising approach for error-tolerant applications to improve hardware performance at the cost of some loss of accuracy. Multiplication is a key arithmetic operation in these applications. In this paper, we propose a low-cost approximate multiplier design by employing new probability-driven inexact compressors. This compressor design is introduced to reduce the height of partial product matrix into two rows, based on the probability distribution of the sum result of partial products. To compensate the accuracy loss of the multiplier, a grouped error recovery scheme is proposed and achieves different levels of accuracy. In terms of mean relative error distance (MRED), the accuracy losses of the proposed multipliers are from 1.07% to 7.86%. Compared with the Wallace multiplier using 40nm process, the most accurate variant of the proposed multipliers can reduce power by 59.75% and area by 42.47%. The critical path delay reduction is larger than 12.78%. The proposed multiplier design has a better accuracy-performance trade-off than other designs with comparable accuracy. In addition, the efficiency of the proposed multiplier design is assessed in an image processing application.

A set of spanning trees of a graphs G are called completely independent spanning trees (CISTs for short) if for every pair of vertices x, y∈V(G), the paths joining x and y in any two trees have neither vertex nor edge in common, except x and y. Constructing CISTs has applications on interconnection networks such as fault-tolerant routing and secure message transmission. In this paper, we investigate the problem of constructing two CISTs in the balanced hypercube BHn, which is a hypercube-variant network and is superior to hypercube due to having a smaller diameter. As a result, the diameter of CISTs we constructed equals to 9 for BH2 and 6n-2 for BHn when n≥3.

Sequences that attain the smallest possible absolute sidelobes (SPASs) of periodic autocorrelation function (PACF) play fairly important roles in synchronization of communication systems, Large scale integrated circuit testing, and so on. This letter presents an approach to construct 16-QAM sequences of even periods, based on the known quaternary sequences. A relationship between the PACFs of 16-QAM and quaternary sequences is established, by which when quaternary sequences that attain the SPASs of PACF are employed, the proposed 16-QAM sequences have good PACF.

We develop a deep neural network (DNN) for detecting driver drowsiness in videos. The proposed DNN model that receives driver's faces extracted from video frames as inputs consists of three components - a convolutional neural network (CNN), a convolutional control gate-based recurrent neural network (ConvCGRNN), and a voting layer. The CNN is to learn facial representations from global faces which are then fed to the ConvCGRNN to learn their temporal dependencies. The voting layer works like an ensemble of many sub-classifiers to predict drowsiness state. Experimental results on the NTHU-DDD dataset show that our model not only achieve a competitive accuracy of 84.81% without any post-processing but it can work in real-time with a high speed of about 100 fps.

An annealing processor based on the Ising model is a remarkable candidate for combinatorial optimization problems and it is superior to general von Neumann computers. CMOS-based implementations of the annealing processor are efficient and feasible based on current semiconductor technology. However, critical problems with annealing processors remain. There are few simulated spins and inflexibility in terms of implementable graph topology due to hardware constraints. A prior approach to overcoming these problems is to emulate a complicated graph on a simple and high-density spin array with so-called minor embedding, a spin duplication method based on graph theory. When a complicated graph is embedded on such hardware, numerous spins are consumed to represent high-degree spins by combining multiple low-degree spins. In addition to the number of spins, the quality of solutions decreases as a result of dummy strong connections between the duplicated spins. Thus, the approach cannot handle large-scale practical problems. This paper proposes a flexible and scalable hardware architecture with time-division multiplexing for massive spins and high-degree topologies. A target graph is separated and mapped onto multiple virtual planes, and each plane is subject to interleaved simulation with time-division processing. Therefore, the behavior of high-degree spins is efficiently emulated over time, so that no dummy strong connections are required, and the solution quality is accordingly improved. We implemented a prototype hardware design for FPGAs, and we evaluated the proposed method in a software-based annealing processor simulator. The results indicate that the method increased the spins that can be deployed. In addition, our time-division multiplexing architecture improved the solution quality and convergence time with reasonable resource consumption.

For the impulse noise removal from a digital image, most of existing methods cannot repair line structures in an input image. In this letter, a method which considers the local line structure is proposed. In order to judge the direction of the line structure, adjacent lines are considered. The effectiveness of the proposed filter is shown by experiments.

This paper proposes a dual-band dual-rectangular-loop circular polarization antenna for Global Navigation Satellite Systems (GNSSs). The proposed antenna combines two large outer rectangular loops with two small inner loops. Each large outer loop is connected to its corresponding small inner rectangular loop. Each loop has gaps located symmetrically with respect to a feed point to produce Right Handed Circular Polarization (RHCP). The gap position and the shape of the rectangular loops are very important to adjust both the impedance matching and circular polarization characteristics. The proposed antenna offers dual-band Voltage Standing Wave Ratio (VSWR) and Axial Ratio (AR) frequency characteristics that include the L1 (1575.42 MHz) and L2 (1227.60 MHz) bands. The antenna gains exceed 8.7 dBi. Broad AR elevation patterns are obtained. These antenna characteristics are well suited to precise positioning.

The performance of a network router/switch has improved significantly over past decades with explosively increasing internet and data center traffic. The performance of a router heavily depends on the memory system, e.g. DRAM based packet buffers, which often limits the scalability of a router. However, a widening gap between memory I/O bus and memory cell array speed and decreasing row buffer locality from increasing channels and banks severely reduce the performance gain from state-of-the-art memory technology such as DDR4 or HBM2 DRAM. Prior works improved memory bandwidth by maintaining SRAM-based per-queue or per-bank input/output buffers in the memory controller to support a DRAM-based packet buffer. The buffers temporarily store packets when bank conflicts occur but are unable to prevent interference-inducing traffic from thrashing DRAM's row buffers. In this study, we directly integrate SRAM into the DRAM-based packet buffer and map those packets degrading row buffer locality of DRAM into SRAM. This maximizes locality and parallelism of DRAM accesses. The proposed scheme can benefit any existing schemes. Experimental results show 22.41% improvement over the best existing scheme for a single channel in terms of the memory bandwidth utilization under harsh congested scenarios.

Towards involving the convolutional neural networks into the object detection field, many computer vision tasks have achieved favorable successes. In order to adapt targets with various scales, deep feature pyramid is widely used, since the traditional object detection methods detect different objects in Gaussian image pyramid. However, due to the mismatching between the anchors and the feature distributions of targets, the accurate detection for targets with various scales is still a challenge. Considering the differences between the theoretical receptive field and effective receptive field, we propose a novel anchor generation method, which takes the effective receptive field as the standard. The proposed method is evaluated on the PASCAL VOC dataset and shows the favorable results.

A Service Function Chain (SFC) is an ordered sequence of virtual network functions (VNFs) to provide network service. Most existing SFC orchestration schemes, however, cannot optimize the resources allocation while guaranteeing the service delay constraint. To fulfill this goal, we propose a Layered Graph based SFC Orchestration Scheme (LGOS). LGOS converts both the cost of resource and the related delay into the link weights in the layered graph, which helps abstract the SFC orchestration problem as a shortest path problem. Then a simulated annealing based batch processing algorithm is designed for SFC requests set. Through extensive evaluations, we demonstrated that our scheme can reduce the end-to-end delay and the operational expenditure by 21.6% and 13.7% at least, and the acceptance ratio of requests set can be improved by 22.3%, compared with other algorithms.

Filter bank multicarrier with offset quadrature amplitude modulation (FBMC-OQAM) is considered an alternative to conventional orthogonal frequency division multiplexing (OFDM) to meet the various requirements proposed by future communication networks. Among the different perspectives on the merits of FBMC-OQAM and OFDM, a straightforward metric is the bit error probability (BEP). This paper presents a general analytical framework for BEP evaluation that is applicable to FBMC-OQAM and OFDM systems in both Rayleigh and Rician multipath fading channels. Explicit BEP expressions are derived for Gray-coded pulse amplitude modulation (PAM) and square quadrature amplitude modulation (QAM) signals with arbitrary constellation sizes. The theoretical analysis results show excellent agreement with the numerical simulation results in different channel scenarios.

We propose a novel compositing pipeline and a dynamic load balancing technique for volume rendering which utilizes a two-layered group structure to achieve effective and scalable load balancing. The technique enables each process to render data from non-contiguous regions of the volume with minimal impact on the total render time. We demonstrate the effectiveness of the proposed technique by performing a set of experiments on a modern GPU cluster. The experiments show that using the technique results in up to a 35.7% lower worst-case memory usage as compared to a dynamic k-d tree load balancing technique, whilst simultaneously achieving similar or higher render performance. The proposed technique was also able to lower the amount of transferred data during the load balancing stage by up to 72.2%. The technique has the potential to be used in many scenarios where other dynamic load balancing techniques have proved to be inadequate, such as during large-scale visualization.

Convolutional neural networks (CNNS) have a strong ability to understand and judge images. However, the enormous parameters and computation of CNNS have limited its application in resource-limited devices. In this letter, we used the idea of parameter sharing and dense connection to compress the parameters in the convolution kernel channel direction, thus greatly reducing the number of model parameters. On this basis, we designed Shared and Dense Channel-wise Convolutional Networks (SDChannelNets), mainly composed of Depth-wise Separable SD-Channel-wise Convolution layer. The advantage of SDChannelNets is that the number of model parameters is greatly reduced without or with little loss of accuracy. We also introduced a hyperparameter that can effectively balance the number of parameters and the accuracy of a model. We evaluated the model proposed by us through two popular image recognition tasks (CIFAR-10 and CIFAR-100). The results showed that SDChannelNets had similar accuracy to other CNNs, but the number of parameters was greatly reduced.

Volleyball video analysis plays important roles in providing data for TV contents and developing strategies. Among all the topics of volleyball analysis, qualitative player action recognition is essential because it potentially provides not only the action that being performed but also the quality, which means how well the action is performed. However, most action recognition researches focus on the discrimination between different actions. The quality of an action, which is helpful for evaluation and training of the player skill, has only received little attention so far. The vital problems in qualitative action recognition include occlusion, small inter-class difference and various kinds of appearance caused by the player change. This paper proposes a 3D global and multi-view local features combination based recognition framework with global team formation feature, ball state feature and abrupt pose features. The above problems are solved by the combination of 3D global features (which hide the unstable and incomplete 2D motion feature caused by occlusion) and the multi-view local features (which get detailed local motion features of body parts in multiple viewpoints). Firstly, the team formation extracts the 3D trajectories from the whole team members rather than a single target player. This proposal focuses more on the entire feature while eliminating the personal effect. Secondly, the ball motion state feature extracts features from the 3D ball trajectory. The ball motion is not affected by the personal appearance, so this proposal ignores the influence of the players appearance and makes it more robust to target player change. At last, the abrupt pose feature consists of two parts: the abrupt hit frame pose (which extracts the contour shape of the player's pose at the hit time) and abrupt pose variation (which extracts the pose variation between the preparation pose and ending pose during the action). These two features make difference of each action quality more distinguishable by focusing on the motion standard and stability between different quality actions. Experiments are conducted on game videos from the Semifinal and Final Game of 2014 Japan Inter High School Games of Men's Volleyball in Tokyo Metropolitan Gymnasium. The experimental results show the accuracy achieves 97.26%, improving 11.33% for action discrimination and 91.76%, and improving 13.72% for action quality evaluation.

This letter presents ternary convolutional codes and their punctured codes with optimum distance spectrum.

This paper constructs non-binary codes correcting a single b-burst of insertions or deletions with large cardinalities. This paper also provides insertion and deletion correcting algorithms of the constructed codes and evaluates a lower bound of the cardinalities of the constructed codes. Moreover, we evaluate a non-asymptotic upper bound on the cardinalities of arbitrary codes which correct a single b-burst of insertions or deletions.

Optical circuits using nanophotonic devices attract significant interest due to its ultra-high speed operation. As a consequence, the synthesis methods for the optical circuits also attract increasing attention. However, existing methods for synthesizing optical circuits mostly rely on straight-forward mappings from established data structures such as Binary Decision Diagram (BDD). The strategy of simply mapping a BDD to an optical circuit sometimes results in an explosion of size and involves significant power losses in branches and optical devices. To address these issues, this paper proposes a method for reducing the size of BDD-based optical logic circuits exploiting wavelength division multiplexing (WDM). The paper also proposes a method for reducing the number of branches in a BDD-based circuit, which reduces the power dissipation in laser sources. Experimental results obtained using a partial product accumulation circuit used in a 4-bit parallel multiplier demonstrates significant advantages of our method over existing approaches in terms of area and power consumption.

We have proposed a generic architecture that can integrate the aspects of confidentiality and integrity into the A/D conversion framework. A conceptual account of the development of the proposed architecture is presented. Using the principle of this architecture we have presented a CMOS circuit design to facilitate a fully integrated Authenticated-Encrypted ADC (AE-ADC). We have implemented and demonstrated a partial 8-bit ADC Analog Front End of this proposed circuit in 0.18µm CMOS with an ENOB of 7.64 bits.