A novel digital signal processing technique fuzzy filtering is proposed for estimating nonstationary signals with ambiguous changes, which are contaminated by additive white Gaussian noises. In this filter, fuzzy clustering is utilized for classifying signal components into groups in which the signal characteristics are considered to be similar. Since the boundary between the signal groups is ambiguous, the fuzzy clustering produces a better effect than crisp clustering. Moreover, robust characteristics are obtained for various values of the parameters and types of processed signals. Computer simulations successfully demonstrate its superior capability of filtering.

We have measured the temperature range ΔTSM of one particular longitudinal mode operation in short-cavity surface emitting (SE) lasers. ΔTSM was increased up to 103 K by reducing the cavity length to be 4 µm. It is expected that a short-cavity SE laser shows stable single mode operation in a wide temperature range.

Estimation of the element values of a minimal RLC network for a specified admittance function may be accomplished by reducing the network to one which can be synthesized by routine methods. There are generally many reduced networks yielding different sets of estimates. Experience shows that the overall estimate, obtained by averaging the values of each element, is the best set of estimates for the element values.

In recent years, communication networks have been required to introduce various services and efficient operation of network resources. There have been many discussions about hierarchical abstraction models of network functions and a distributed application platform, such as studies of the intelligent Network conceptual model and Distributed Application Framework in CCITT. On the other hand, communication networks (telecom networks, packet switching networks, common channel signaling networks and intelligent networks) will be integrated in Asynchronous Transfer Mode (ATM) nodes in the future B-ISDN era. Each communication network will be constructed on an integrated transport network. This paper proposes the new concept of "Software Defined Architecture (SDA) ", a conceptual model for implementing communication networks and a network system model for describing communication networks. This concept makes possible communication networks that can be quickly constructed in an integrated transport network and dynamically reconstructed in response to traffic fluctuations and node overloads. Using the network system model, a network system is specified by three kinds of specifications: component, frame and implementation. The network system is constructed or reconstructed on the basis of these specifications. This paper reports an intelligent network system as an example of a communication network which applies the SDA concept.

We propose a single-chip 400-MFLOPS 2-D FFT processor VLSI architecture. This processor integrates 380,000 transistors in an area of 11.5811.58 mm2 using 0.8 µm CMOS technology with a typical machine cycle time of 25 ns, and executes 2n2n point 2-D FFT in real time, e.g., 256256 point FFT is executed in 14 ms. This excellent performance in terms of both speed and dynamic range makes the real-time processing practical for video as well as speech processing.

Some dedicated floating-point hardware arithmetic modules designed as processing elements for butterfly operations are described. They consist of Input Data Converters (IDC), Output Data Converters (ODC), and a 2's complementary 24-bit (16E8) floating-point Butterfly Execution Unit (BEU). The BEU executes the four multiplication and six additions/subtractions required for a complex butterfly operation in each 25-ns execution cycle by implementing four multipliers and four 3-input adders/subtracters. The arithmetic modules are fabricated using 0.8-µm CMOS technology. An overview of the hardware unit is presented with special attention given to the BEU for parallel pipelined processing. In addition, module design methodologies for hardware implementation and some sophisticated high-speed execution techniques for floating-point multiplication and addition are discussed.

A challenge-and-response type identification protocol consists of three moves of messages between a prover and a verifier: Move-1--The prover claims to the verifier that his/her identity is ID. Move-2--The verifier challenges the prover with a question related to the ID. Move-3--The prover responds with the answer of the question. The verifier accepts the prover if the answer is correct. The main contribution of this paper is to show that the folklore can be made provably secure under the sole assumption of the existence of one-way functions.

In a large scale distributed environment or large open networks like WIDE Internet which is an academic and reserch network in Japan, the authentication system is the fundamental building block for providing security mechanisms. We have developed a trusted third-party authentication system called SPLICE|AS for the WIDE Interet. The authetication protocol adopted in SPLICE|AS is based on the public-key encryptosystem, originally proposed by Needham. We made several extensions to detct some sort of security attacks like replay attacks which were not considered in the original Needham's approach. Furthermore, the domain-based management scheme and protocol extensions are introduced to our system since management principals are scatterd across the WIDE Internet. The whole network is logically subdivided into several domains based on network management policies, and each domain is managed by a single authentication server. Then, the domain concept is applied in a hierarchical manner to provide the inter-domain access. An authentication server existing in an upper domain authorizes and controls inter-domain accesses between subdomains. This paper describes the design of SPLICE|AS, and its implementatins.

A 1.3 µm DFB-LD module was developed for multi-channel AM transmission systems. The relationships between laser characteristics and carrier to noise ratio (CNR), composite second order distortion (CSO) and composite triple beat (CTB) in 42-channel analog AM transmission experiments using a 15km single-mode fiber were investigated. To achieve a CSO value lower than --62dBc the laser l-L curve linearity should be less than 5%. The relation between CSO and the number of second order intermodulation products was theoretically and experimentally investigated. To achieve a CNR bigger than 52dB (4MHz), the relative intensity noise (RIN) value of the laser should be less than --155dB/Hz as predicted in a theoretical model. The lowest CSO and CTB values were obtained by optimizing the laser bias current at a certain modulation depth. There was a trade-off between CSO, CTB and CNR in optimizing the laser bias current and modulation depth.

The group-delay sensitivity is studied theoretically for Gray and Markel allpass lattice filter realizing complex transfer function. Recursive expressions which were derived for phase and group-delay in real lattice are rederived for the complex case. These expressions are used to obtain upper bounds on group-delay sensitivity. The minimum number of frequencies where group-delay sensitivity becomes zero is discussed. Results corresponding real allpass lattice are also shown. Phase sensitivity properties of these filters are analyzed and compared with existing results. A new bound on phase sensitivity is also obtained.

As the telecommunications network evolves to provide a greater variety of services and incorporate new technologies under the increasing multi-vendor environment, it has become important to ensure that the network evolves gracefully. As part of the endeavor to ensure this graceful evolution, Nodal System Architecture has been studied and applied. It aims to standardize the interface between communications systems, called modules in the Architecture, located in the same building. This paper describes the requirements that are considered in specifying Nodal System Architecture. Namely, the paper describes the classification of network functionality for determining functions allocation to modules, and the needs for defining the conditions for being a module, and estimates the volumes of three types of information that flow through inter-module interfaces for determining the protocol structure to be used for each type of information. Finally, the paper presents examples of inter-module links for different node sizes.

Superscalar processors can improve uniprocessor performance further byond RISC performance by exploiting spatial instruction-level parallelism. Superscalar processor design presents more opportunities for tradeoffs than conventional RISC design. In order to utilize processor resources augmented by the superscalar approaches, processors must be carefully designed and implemented. This paper examines the various aspects of superscalar processors and discusses the design features and tradeoffs. Specific aspects of superscalar processors that are examined include: instruction fetch boundary, instruction-cache line crossing, branch prediction, data-hazard resolution, control-hazard resolution, and precise or imprecise interrupts. This paper uses a superscalar simulator that modeled a DDU (Dynamically-hazard-resolved, Dynamic-code-scheduled, Uniform) superscalar architecture, called SIMP (Single Instructions stream/Multiple instruction Pipelining), and evaluate many different SIMP hardware organizations. This paper concludes that a superscalar processor can increase the performance with major five hardwary features: instruction aligning, branch prediction with branch-target buffer, code scheduling, speculative execution with conditional mode, and imprecise interrupts. However, the first three functions are claimed to be performed by compilers rather than by hardware.

This paper details a unique VLSI design scheme which employs self-timed circuits. A 32-bit 50-MFLOPS data-driven microprocessor has been designed using a self-timed clocking scheme. This high performance data-driven microprocessor with sophisticated functions has been designed by a combination of several kinds of self-timed components. All functional blocks in the microprocessor are driven by self-timed clocks. The microprocessor integrates 700,000 devices in a 14.65 mm14.65 mm die area using double polysilicon double metal 0.8 µm CMOS technology.

A bus system whose configuration can be dynamically changed is called a reconfigurable bus system. A reconfigurable array consists of processors arranged to a 2-dimensional grid with a reconfigurable bus system. We present a parallel algorithm which sorts N elements in O (T) time on a reconfigurable array with NN log(T) N processors for every Tlog*N.

A method to estimate picture quality by two-dimensional perceptive power using visual modulation transfer function including its oblique function was studied. First, visual modulation transfer functions measured conventionally were reviewed and its new formulae including spatial anistropy was presented. Using these formulae, picture quality estimation method was discussed. This method was verified by picture quality with horizontal signal band limitation. As the application of this method, line-offset sub-sampling for lower level family of digital television coding below 4:2:2, progressive scanning conversion for EDTV receiver and luminance resolution expansion through field-offset sub-sampling for EDTV were discussed and good efficiencies of this method for the signal processing design was shown.

Image labeling is a process of recognizing each segmented region properly exploiting the properties of the regions and the spatial relationsships between regions. In some sense, image labeling is an optimization process of indexing regions using the constraints as to the scene knowledge. In this paper, we further investigate a method of efficiently labeling images using the Markov Random Field (MRF). MRF model is defined on the region adjacency graph and the labeling is then optimally determined using the simulated annealing. To endow the adaptability to the MRF-based image labeling, we have proposed a parameter estimation technique based on error backpropagation. We analyze the proposed method through experiments using the real natural scene images.

Modular design of concurrent systems can be based on concrete net composition techniques. For example, to design a discrete event systems with some desirable properties such as liveness and safeness by composition of simple subsystems (modules), specific rules of composition have to be found. Unfortunately, there exist no general techniques to guarantee the overall properties by net composition except for a restricted case of the stepwise refinement. In this paper, we conduct a necessary and sufficient condition for a net composition to guarantee the composed net fallen into an important subclass of Petri nets. A free choice nets is a class of Petri nets, which can represent the substantial feature of systems by modeling both choice and concurrency. A state machine decomposable nets (SMD nets) is a class of nets composed by a set of strongly connected state machines (SCSMs). A state machine allocatable nets (SMA nets) is a class of SMD nets in which the way of SCSM composition is implicitly restricted by the definition. The structural characterization of SMA nets has originally been considered by Hack. The aim of this paper is to clarify the restrictions on SCSM composition for SMA nets and to derive the complete structural characterization of this class of nets. The problem can be viewed as to find the structure of the synchronization between SCSMs to yield relevant properties such as SMA nets. Esparza and Silva have investigated the same problem and derived a necessary and sufficient condition for a net to be an SMA net. The condition obtained in this paper is more explicit and simple with respect to the way of SCSM composition. The importance of investigating the structural properties of SMA net can be understood by the fact that a free choice net is live and safe if and only if the net is an SMA net, and to synthesize a live and safe free choice net is often the goal of correct concurrent system design.

Nonlinear operation of an analog frequency divider using a GaAs dual-gate FET has been studied theoretically and experimentally. It is shown that the log-log plot for basic input/output characteristics of the divider shows straight lines in the second, third, and fourth regions adjacent to the first narrow threshold region in the increasing order of input power magnitude. It is suggested from theoretical consideration that universality of the exponent K appearing in the PoutPinK relation holds at least approximately. The value of K in the second region is found to be about 3.0 theoretically and experimentally and is in agreement with the value reported in an earlier paper. The strict but obvious universality of K holds in the third and fourth region with K=1 and 0, respectively.