Multicast routing problem is one of the essential problems for supporting multicast and broadcast communication service which is the most important service of the multimedia information networks. Multicast routing is the problem of finding out an adequate path which connects one source node and more than one destination node, i.e. a tree shaped path. In packet type networks, a packet for multicast communication should go through the tree shaped path as making its copies at a branching node for efficient use of network resources. However, concentration of packet copy operations at a particular node leads to performance degradation of other calls which go through this node. In this paper we propose two multicast routing algorithms which distribute packet copy operations through whole nodes in the multicast path; a link added type algorithm and a loop constructed type algorithm. Both algorithms, at first, find out an approximate solution for minimum cost path, and avoid concentration of packet copy operation at a little sacrifice of total cost in the path. Computer simulation results show that these algorithms can decrease the burden of packet copy operation per a node at the sacrifice of increase in average distance (cost) of a source-destination pair but the sacrifice of total cost is very small.

This paper presents further results on the circular Levinson algorithm for multichannel linear prediction consisting only of scalar operations. The first result is an explicit inversion formula of the covariance matrix. This is a generalization of Trench and Gohberg-Semencul formula. An application to time series modeling is also mentioned. The second one is a simple modification in the algorithm to treat the case where the covariance matrix becomes singular. An example is given how the modified algorithm works.

Network management technologies based on network-wide real-time control schemes have become significant in ensuring both high throughput and GOS fairness and maintaining high usage of network facilities. The first part discusses the roles of network control schemes in the network resource hierarchy. With respect to the layering concept for network resources, it is clarified as to why each network control scheme should maintain its autonomy in each corresponding network resource layer, as well as cooperate with the other control schemes. Examples of cooperative control are presented to show that both dynamic routing in the circuit layer networks and path assignment control in the path layer networks can mutually compensate each other for any insufficient control. In the second part, an advanced routing scheme called "State- and Time-dependent Routing (STR) " is proposed. The principle of STR is a combination of routing-domain definition on a time-dependent basis and call-level routing on a state-dependent basis. Performance evaluation examples of STR through large-scale call-by-call computer simulations are presented to show its high throughput performance as well as high adaptability to real-time traffic fluctuations. A system configuration example featuring the STR algorithm which is currently under development for use in NTT's transit networks is also shown.

A discrete and near-uniform arrival (DNA) model is proposed to analyze a statistical voice packet multiplexer. The DNA model assumes that the arrival process of aggregate voice packets from several voice sources in talkspurt be in a discrete mode with near-uniform distribution over a packetization time. Finite queue size for the statistical voice packet multiplexer is also assumed. Results of the probability distribution functions of the queue length and the packet delay are obtained; the optimal packet length is also determined by the 99.9th percentile of delay.

This paper presents a new method for implementing modem by using a periodically time varying digital filter. Firstly, we present that a modulation and a demodulation are realized by using a periodically time varying digital filter (abbreviated to a PTV filter). Next, we present that these functions of a modem can be implemented in one PTV filter. Generally, it is very complicated to search the shifted carrier frequency of a transfered modulated signal. Since only a PTV filter are used in the proposed system, we do not need to search the shifted carrier frequency in modem. So, the proposed method is better than the conventional method in this point.

The full band inverse fiter of an acoustic field usually can not be approximated by causal filter because of its non-minimum phase property. However, by dividing the full band signal into many sub-bands, most of the sub-bands, that do not have zeros extremely close to or outside of the unit circle, can be inverted by causal filter. In this paper, a method of recovering the reverberated speech signals by sub-band envelope estimation is proposed. A reference signal and its reverberated version are supposed to be known at the parameter estimation phase. Both signals are divided into many sub-bands. The dereverberation filter for each sub-band is calculated by the least mean square extimation of the reference sub-band signal from the reverberated one. Reverberated signals under the same condition can be recovered using the estimated dereverberation filters. Comparison of the dereverberation error and distribution of the room transfer function zeros showed that the sub-bands that have large dereverberation errors are those with zeros extremely close to or outside of the unit circle. The performance of the dereverberation is improved with the increase of the number of sub-bands. The reverberated speech is recovered in good quality when the reverberation time is less than 0.43s, which is approximately the reverberation condition of the general small office rooms.

In a large scale distributed environment or large open networks like WIDE Internet which is an academic and reserch network in Japan, the authentication system is the fundamental building block for providing security mechanisms. We have developed a trusted third-party authentication system called SPLICE|AS for the WIDE Interet. The authetication protocol adopted in SPLICE|AS is based on the public-key encryptosystem, originally proposed by Needham. We made several extensions to detct some sort of security attacks like replay attacks which were not considered in the original Needham's approach. Furthermore, the domain-based management scheme and protocol extensions are introduced to our system since management principals are scatterd across the WIDE Internet. The whole network is logically subdivided into several domains based on network management policies, and each domain is managed by a single authentication server. Then, the domain concept is applied in a hierarchical manner to provide the inter-domain access. An authentication server existing in an upper domain authorizes and controls inter-domain accesses between subdomains. This paper describes the design of SPLICE|AS, and its implementatins.

A method to estimate picture quality by two-dimensional perceptive power using visual modulation transfer function including its oblique function was studied. First, visual modulation transfer functions measured conventionally were reviewed and its new formulae including spatial anistropy was presented. Using these formulae, picture quality estimation method was discussed. This method was verified by picture quality with horizontal signal band limitation. As the application of this method, line-offset sub-sampling for lower level family of digital television coding below 4:2:2, progressive scanning conversion for EDTV receiver and luminance resolution expansion through field-offset sub-sampling for EDTV were discussed and good efficiencies of this method for the signal processing design was shown.

In this letter, we consider the following problem: Given a weighted digraph G=[V, EaEb] such that subgraph Ga=[V, Ea] of G is an acyclic graph with a single source vertex and the weight of each edge in Eb is negative, if G has a positive cycle, then locate them as many as possible; otherwise, compute the longest path length from source vertex to each vertex of V. Then, we propose an algorithm to this problem and show some experimental results to demonstrate the efficiency of the proposed algorithm.

Superscalar processors can improve uniprocessor performance further byond RISC performance by exploiting spatial instruction-level parallelism. Superscalar processor design presents more opportunities for tradeoffs than conventional RISC design. In order to utilize processor resources augmented by the superscalar approaches, processors must be carefully designed and implemented. This paper examines the various aspects of superscalar processors and discusses the design features and tradeoffs. Specific aspects of superscalar processors that are examined include: instruction fetch boundary, instruction-cache line crossing, branch prediction, data-hazard resolution, control-hazard resolution, and precise or imprecise interrupts. This paper uses a superscalar simulator that modeled a DDU (Dynamically-hazard-resolved, Dynamic-code-scheduled, Uniform) superscalar architecture, called SIMP (Single Instructions stream/Multiple instruction Pipelining), and evaluate many different SIMP hardware organizations. This paper concludes that a superscalar processor can increase the performance with major five hardwary features: instruction aligning, branch prediction with branch-target buffer, code scheduling, speculative execution with conditional mode, and imprecise interrupts. However, the first three functions are claimed to be performed by compilers rather than by hardware.

New OTA-based analog circuits for realizing fuzzy membership functions and maximum (MAX) and minimum (MIN) operations are proposed. The synthesis of these circuits based on a bounded-difference operation and their SPICE simulations are described.

A 64 b CMOS mainframe execution unit macrocell with error detecting circuits is proposed. The conventional techniques to maintain high reliability have been the parity checking and the duplication of the ALU (Arithmetic Logic Unit). However, the required time for generating the parity from the sum output of the ALU has been undesirable for high-speed operation. In order to achieve a short ALU delay time, a parity predicting logic structure is newly adopted. By utilizing this structure, a one-bit-error detecting function is integrated without duplicating the every ALU circuit. A novel CMOS precharged circuit is also developed to shorten the time required to precharge the whole circuit. When the number of circuit stages is reduced, the precharge time as well as the delay time restricts the ALU cycle time. This new circuitry solves the precharging time accumulation problem in the conventional circuits. A 64 b BCD ALU adopting this technology has been designed and fabricated. The parity predict architecture and the high-speed-precharge circuit have been effective in reducing the delay time by 23% and the precharge time by 42%. A 30% faster cycle time has been achieved with a small increase (4%) in ALU area. The execution unit macrocell, which includes the ALU described above, contains 45 k transistors and it's area is 4.3 mm4.1 mm using the 0.8 µm CMOS triple metal layer technology.

We have newly developed a VLSI intelligent cache memory chip which constitutes one processor element of a Parallel Inference Machine (PIM/m) system. This cache memory chip contains 610 k transistors including 80 kbits memory cells. The chip measures 14.47 mm14.84 mm and is fabricated by using 1.0µm CMOS double metal technology. The cache memory chip implements a hardware support called "Trail Buffer" which is suitable for the execution of logic programming languages. We have determined the cache memory size by practical simulation taking the relationship between the chip size and hitratio of the cache memory into consideration. The scan test method and the special commands to access every memory cell are applied to enhance the testability. This chip itself operates at a cycle time of 30 MHz. The typical power consumption is 2.5 W with a 5.5 V power supply at 16.7 MHz operation. With this cache memory chip, the CPU board of the PIM/m is now tuned for 16.7 MHz operation and has attained 1.5 MLIPS (logical inference per second), which is the highest performance as an inference machine in the world.

This paper describes circuit techniques of a 5 ns, 4 kw9 b embedded RAM for standard cell ASICs applying 0.8 µm pure CMOS triple metal technology. The design goals of the above techniques were high speed, low power consumption, and access time stability even when the RAM configuration is changed in word and bit numbers. A one-chip 4,096-channel time switch VLSI for digital switching systems is also described as an example of application of these RAMs to standard cell CMOS ASICs. This chip has 600 mW power consumption during 32 MHz operation.

This paper details a unique VLSI design scheme which employs self-timed circuits. A 32-bit 50-MFLOPS data-driven microprocessor has been designed using a self-timed clocking scheme. This high performance data-driven microprocessor with sophisticated functions has been designed by a combination of several kinds of self-timed components. All functional blocks in the microprocessor are driven by self-timed clocks. The microprocessor integrates 700,000 devices in a 14.65 mm14.65 mm die area using double polysilicon double metal 0.8 µm CMOS technology.

This paper describes a new method of state extimation for the energy stochastic system with decibel observation mechanism. The problem here is to get the decibel-valued estimate of the energy state variable through the decibel-valued noisy observation data, where it is usual that the stochastic system is physically driven on energy scale. The main attention is paid to the adjustment between the energy quantity at the physical countermeasure side and the decibel quantity at the human evaluation side. The basic principle of state estimation is based on the Bayes' theorem which can be applicable to any non-Gaussian and/or non-linear nature of the real stochastic system. Then, it is expanded into the suitable form adapted to successive decibel-valued observation. Thus, based on the mutual relation between energy and decibel statistics, any kinds of statistics connected with Lx evaluation at the human side can be estimated by using this decibel-valued noisy observation data (Lx is defined in the acoustics field as the (100-x)% point of the sound-level distribution and it is often used as the environmental noise assessment standard because man's sense of hearing is very sensitive to the end of the sound-level distribution form). Finally, the validity and the effectiveness of the proposed method have been confirmed by application to the actually obtained room acoustics data.

A 1.3 µm DFB-LD module was developed for multi-channel AM transmission systems. The relationships between laser characteristics and carrier to noise ratio (CNR), composite second order distortion (CSO) and composite triple beat (CTB) in 42-channel analog AM transmission experiments using a 15km single-mode fiber were investigated. To achieve a CSO value lower than --62dBc the laser l-L curve linearity should be less than 5%. The relation between CSO and the number of second order intermodulation products was theoretically and experimentally investigated. To achieve a CNR bigger than 52dB (4MHz), the relative intensity noise (RIN) value of the laser should be less than --155dB/Hz as predicted in a theoretical model. The lowest CSO and CTB values were obtained by optimizing the laser bias current at a certain modulation depth. There was a trade-off between CSO, CTB and CNR in optimizing the laser bias current and modulation depth.

As the telecommunications network evolves to provide a greater variety of services and incorporate new technologies under the increasing multi-vendor environment, it has become important to ensure that the network evolves gracefully. As part of the endeavor to ensure this graceful evolution, Nodal System Architecture has been studied and applied. It aims to standardize the interface between communications systems, called modules in the Architecture, located in the same building. This paper describes the requirements that are considered in specifying Nodal System Architecture. Namely, the paper describes the classification of network functionality for determining functions allocation to modules, and the needs for defining the conditions for being a module, and estimates the volumes of three types of information that flow through inter-module interfaces for determining the protocol structure to be used for each type of information. Finally, the paper presents examples of inter-module links for different node sizes.

VLSI implementation of the network for a highly parallel computer system by three ASIC chip-set and some related results are described. The chip-set consists of two network-component chips, BMU and SRC, with which the crossbar-like network of arbitrary size can be realized, and a versatile network controller, TCU. New FIFO circuit, inter-chip pipelined data transmission scheme and novel cooperation method between computation and communication called 'FIFO emulation' were introduced in conjunction with communication overheads in parallel processing to enhance effective computing performance and actual transfer rate. The chip set employs synchronous 9 bit bus with peak date transmission rate of 20 MB/sec/channel. All chips are fabricated in 1.2 µm two layer AL N-well CMOS technology, containing 350 k, 25 k and 165 k transistors, respectively. Experiments shows that measured communication overhead is less than 30% where the ratio of computing in MFLOPS and communication in Mword/sec was 1, and 'FIFO emulation' scheme reduces communication time by 21% in the same case.