A photonic switching system is expected to have advantages over a conventional electronic switching system in exchanging broadband signals. Extensive studies have recently done on various photonic switching systems. State-of-art technology in photonic switching systems is surveyed in this paper. Small-capacity space-division switching systems using waveguide optical matrix switches are most practical and expected to be introduced to broadband local-area network in the near future. Wavelength division switching technology is important in extending switching capacity to large value. Application of photonic switching technology for ATM switching systems is also recently extensively studied to achieve switching throughput larger than that of electronic ATM switches.

In this paper, we discuss the weak point of a conventional bypass circuit, or carry-skip paths in a Manchester adder, and propose a new bypass circuit and its control scheme to avoid transitory fighting that causes an intermediate voltage. A 112-b transmission gate adder is presented, which uses a group of three mutually exclusive transmission gates for the carry-skip paths and a new conditional sum generation circuit. It has an estimated propagation delay time of 8.5 ns and 6941 transistors, both of which are smaller than those of conventional carry select adders. The adder is integrated into an area of 0.41 3.36 mm2 achieved by a 0.8-µm, triple-metal, full-CMOS process.

It is known that the uniquely decodable code pairs (C1, C2) for the two-user binary adder channel relates to the maximum independent set of a graph associated with a binary code. This paper formulates the independence number of a class of graphs associated with binary linear codes, and presents an algorithm of the maximum independent set for those graphs. Uniquely decodable code pairs (C1, C2)'s are produced, where C1 is a linear code and C2 is a maximum independent set of the graph associated with C1. For the given C1, the transmission rate of C2 is higher than that by Khachatrian, which is known as the best result as so far. This is not rather surprising because the code C2 is a maximum independent set in this paper but not be Khachatrian's.

A closure test MCT (meet-in-the-middle closure test) has been introduced to analyze the algebraic properties of cryptosystems. Since MCT needs a large amount of memory, it is hard to implement with an ordinary meet-in-the-middle method. As a feasible version of MCT, this paper presents a switching closure test SCT based on a new memoryless meet-in-the-middle method. To achieve the memoryless method, appropriate techniques, such as expansion of cycling detection methods for one function into a method for two functions and an efficient intersection search method that uses only a small amount of memory, are effectively used.

This paper deals with the problem of assigning tasks to the processors of a multiprocessor system such that the sum of execution and communication costs is minimized. If the number of processors is two, this problem can be solved efficiently using the network flow approach pioneered by Stone. This problem is, however, known to be NP-complete in the general case, and thus intractable for systems with a large number of processors. In this paper, we propose a network flow approach for the task assignment problem in homogeneous hypercube networks, i.e., hypercube networks with functionally identical processors. The task assignment problem for an n-dimensional homogeneous hypercube network of N (=2n) processors and M tasks is first transformed into n two-terminal network flow problems, and then solved in time no worse than O(M3 log N) by applying the Goldberg-Tarjan's maximum flow algorithm on each two-terminal network flow problem.

A high-performance CMOS line driver for ISDN U-interface transceiver applications has been designed and fabricated. Careful study of requirements and trade-offs affecting linearity, power efficiency, and quiescent current presented in this paper has resulted in a circuit structure featuring a highly linear input/output characteristic and well-controlled quiescent current. The prototype line driver is capable of delivering a 5Vpp signal of up to 80 kHz to a 60-Ω load while exhibiting linearity in the order of 77 5 dB and operating from a single 5-V power supply. Linearity better than 70 dB is maintained for load resistances as low as 20 Ω.

A multihighway serial/parallel (S/P) converter LSI chip suitable for the broad-band Integrated Services Digital Network (B-ISDN) node interface is presented. The chip, fabricated with 0.8-µm BiCMOS technology, handles 32-highway 8 b of S/P, P/S conversion at up to 250 Mb/s and has a power dissipation of 700 mW. The features cross-access memory and a current-cut-type CMOS/ECL interface circuit. Each of these features is described and evaluated. A newly developed BiNMOS-type D-flip-flop (D-FF) is used to speed up the cross-access memory and is compared to a CMOS D-FF.

According to the development of optical communication technologies, it is getting easier to handle new devices, such as optical fibers, semiconductor light sources, guided wave devices, and optical integrated circuits. These devices have recently given considerable impact on the optical sensing field. The optical sensing shares the optical devices and the concepts of signal processing or system configuration with the optical communication. In this paper, the advanced lightwave sensing technology is discussed, considering the relation to the advanced optical communication technology. Distributed fiber sensors and the application of coherence characteristics of semiconductor light sources are the topics to be mainly discussed. In the distributed fiber sensors, the fiber plays both a role of low-loss transmission line and a role of lengthwise deployed sensing element. According to the change of characteristics of light propagating in the fiber, distribution of various physical parameters can be measured, such as the fiber loss, temperature, and strain. Optical Time Domain Reflectometry is employed to determine the location. Another tendency in the lightwave sensing field is the use of coherence characteristics of various semiconductor light sources. Low coherent source provide a highly sensitive inertial rotation sensor, that is, interferometric fiber optic gyroscope. Another type of optical gyroscope, optical passive ring-resonator gyro, has been studied as an application of a high coherence source. Frequency tunability of the semiconductor laser, especially that of tunable DFB or DBR lasers, can provide new ways in signal processing in the sensors. Optical coherence function can be synthesized also by utilizing the tunability. In conjunction with the progress in optical communication, lightwave sensing fields are steadily increasing.

A family of user-programmable peripherals, utilizing an integration strategy based on a programmable system device (PSD) concept, is described. Specifically, PSD is an efficient and highly configurable integration of high-density memory and LSI level logic blocks. The configurability is derived by providing programmable logic and programmable interconnect. PSDX is the first PSD family of programmable microcontroller peripherals; it integrates 256 kb to 1 Mb of EPROM, 16 kb of SRAM, a 28-input by 42-product term programmable logic device (PLD), and flexible I/O ports. This family is primarily targeted for embedded microcontroller applications. Using one PSD device it is possible to replace all the core peripherals in the system and, as a result, achieve a reduction in components, power dissipation, and overall system cost. The flexible architecture is achieved by providing 46 configuration options, which allows the PSD to interface with virtually any 8- or 16-b microcontroller. The integration is made possible by developing a special configurability and testability scheme. These parts are realized on a 1.2-µm CMOS EPROM process which includes an NVM module that provides the dedicated cells for the EPROM (10.6 µm2), PLD, and the configuration bits. The die size is 46 mm2 (for PSD2, which contains 512-kb EPROM) and is housed in a 44-pin package. Memory access time through the PLD is 120 ns and the PLD pin-to-pin delay is 35 ns at 4.5 V and 75.

This paper describes a real-time degradable four-way set-associative cache memory control (CMC) LSI. Three kinds of errors, address parity error, comparator error, and multihit error, can cause functional degradation by killing the associative unit corresponding to the fault location. A 20-b tag parity generator, a double comparator, and a multihit detector are the key circuits for the fault detection. The parity generator and the double comparator have no effect on the timing-sensitive path delay because of the parallel configuration of the circuits. The multihit detector occupies about 16% of the propagation delay of the critical path, from the external address input to the hit/miss output.

This paper examines the key technologies and applications of optical frequency division multiplexing (OFDM) systems. It is clarified that a 100-channel OFDM system is feasible as a result of multichannel frequency stabilization, common optical amplification and channel selection utilizing a tunable optical filter. Transmission limitation due to fiber four-wave mixing is also described. Major functions and applications of the OFDM are summarized and the applicability of OFDM add/drop multiplexing is examined.

Relaxation-type monolithic silicon bipolar voltage-controlled oscillators (VCO's) with center frequencies ranging from 1.5 to 5 GHz are described. The maximum oscillating frequency achieved is 7.4 GHz. The VCO's dissipate about 70 mW from a 3.6-V supply, including the output buffer and voltage-to-current converter stages. Two types of on-chip timing capacitor structures and various configurations used in achieving these results are described. A wide tuning range has been achieved which is sufficient to cover the normal process tolerances and supply variations expected in a practical environment. The circuits are fabricated in an advanced 0.8-µm double-poly self-aligned bipolar technology.

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25-µm BiCMOS technology. A pair of ECL/CMOS level converters with build-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance.

Conventionally, ultrahigh-speed 2:1 multiplexers and 1:2 demultiplexers have been demonstrated with HBT's, MESFET's, and Si BJT's. Multiplexers and demultiplexers with a high number of bits are desirable to simplify a system. An 8:1 multiplexer and a 1:8 demultiplexer operating at 6 Gb/s and a 16:1 multiplexer and a 1:16 demultiplexer operating at 10 Gb/s were realized by HBT's and MESFET's, respectively. This paper describes Si bipolar circuits and package design technology for a 5-Gb/s 8:1 multiplexer and a 4.2-Gb/s demultiplexer. These multigigabit LSI's have been mainly achieved by switching current optimization within the limit of keeping a maximum unity unilateral gain frequency (fmax), by careful circuit and layout design considering accurate parasitic capacitance modeling, and by using a high-speed Si bipolar technology. These LSI's are housed in a newly developed 56-pin six-layer ceramic package with chip resistors for ECL termination and chip capacitors for good RF grounding.

A frame-installed lightwave synthesizer is constructed for optical frequency-division-multiplexing (FDM) communication. The synthesizer consists of two DFB diode lasers, electrical feedback loops, and an HCN gas cell used as a frequency reference at v0=192,843GHz (1.55459µm in wave-length). Output frequency can be stabilized at anywhere within v0(220) GHz. The beat note observed between the synthesizer and another HCN-stabilized DFB laser is constant within 2MHz over 100 hours. Frequency stability better than 410-10 (80kHz, without normalization) is obtained for an averaging time of 200s.

An application of wavelength conversion laser diodes (WCLDs) to a photonic cross-connect system using wavelength-division (WD) technology is presented. We propose a novel WD photonic cross-connect node architecture with multiwavelength selective filters. By using the filters, we can construct a nonblocking cross-connect switch by 2-stage connection. Next we describe the requirements to the optical devices in our switch, especially to the wavelength conversion devices in configuring a multistage connection of our switch. Finally, we have conducted the wavelength switching experiments using our wavelength conversion laser diode at a bit rate of 125Mb/s and shown its applicability to a WD photonic cross-connect system with over 3,000 channels.

A high-gain wide-band amplifier IC module is needed for high-speed communication systems. However, it is difficult to expand bandwidth and maintain stability. This is because small parasitic influences, such as bonding-wire inductance or the capacitance of the package, become large at high frequencies, thus degrading performance or causing parasitic oscillation. In this paper, a new design procedure is proposed for the high-gain and wide-band IC module, using stability analysis and a unified design methodology for IC's and packages. A multichip structure is developed using stability analysis and the requirements for stable operation are determined for each IC chip, package, and interface condition between them. Furthermore, to reduce the parasitic influences, several improvements in the interface and package design are clarified, such as wide-band matching and LC resonance damping. IC design using effective feedback techniques for enlarging the bandwidth are also presented. The IC's are fabricated using 0.2-µm GaAs MESFET IC technology. To verify the validity of these techniques, an equalizer IC module for 10-Gb/s optical communication systems was fabricated achieving a gain of 36 dB and a bandwidth of 9 GHz.

This paper presents novel temperature-compensation circuit techniques for the CMOS DRAM internal voltage converter, the RC-delay circuit, and the back-bias generator, which do not need any additional process steps. The abovementioned circuits have been designed and evaluated through a 16-Mb CMOS DRAM. These circuits have shown an internal voltage converter (IVC) with an internal voltage temperature coefficient of 185 ppm/, and an RC-delay circuit with a delay time temperature coefficient of 0.03%/. As a result, 6.5-ns faster RAS access time and improved latch-up immunity have been achieved, compared with conventional circuit techniques.

This paper describes a new biasing scheme for sensing circuits, namely an automated bias control (ABC) circuit, for high-performance VLSI's. The ABC circuit can automatically gear the output level of sensing circuits to the input threshold voltage of the succeeding CMOS converters. The sensing performance can be accelerated with the ABC circuit either by reducing excessive signal level margin between the sensing circuits and the CMOS converters or by reducing extra stage of signal amplification. Since feedback control of the ABC circuit ensures a correct dc biasing even under large process deviation and circuit condition changes, wider operation margin can also be obtained. Three successful applications of the ABC circuit are reported: a sense amplifier, an address transition detector (ATD), and an ECL-CMOS input buffer. A 64-kb BiCMOS SRAM employing the proposed sense amplifier and the ATD has been fabricated with a 0.8-µm 9-GHz BiCMOS technology. The SRAM has an address access time of 4.5 ns.