In this paper, we propose a new design technique called extit{asynchronous multi-frequency clocking} for suppressing EMI at a chip design level by combining two independent EMI-suppressing approaches: extit{multi-frequency clocking} and extit{asynchronous circuit design} techniques. To show the effectiveness of our approach, a five-stage pipelined asynchronous MIPS with multi-frequency clocking has been implemented on a commercial Xilinx FPGA device. Our approach shows 11.05 dB and 5.88 dB reductions of peak EM radiation in the prototyped implementation when compared to conventional synchronous and bundled-data asynchronous circuit counterparts, respectively.

Wireless sensor networks (WSNs) consist of numerous wireless sensor nodes, each sensor node embedding a tiny communication device enabling the nodes to communicate with each other or the base station. In this paper, we investigate the problem that communication distance must be considered in minimizing the wireless communication energy since the energy consumption is proportional to the 2nd to the 6th power of the distance. Moreover, another problem is that there is a non-uniform energy drain effect in most topologies. Known as the energy hole problem, it can result in premature termination of the entire network. To address these problems, in this paper we first propose a communication routing algorithm that can solve the energy hole problem to the maximum extent possible while minimizing the wireless communication energy by generating an energy efficient spanning tree. This algorithm is beneficial for network lifetimes defined by a high node termination percentage. For the WSNs for which the energy hole problem is critical, we propose two route switching algorithms to solve the energy hole problem; they are beneficial for network lifetimes defined by a low node termination percentage. Simulation results showed that these algorithms avoid the energy hole problem and thereby greatly extend the lifetime of WSNs by more than 3 to 6 times that of ones using direct transmission in a 20-node network and a 50-node network if the lifetime of a WSN is defined by 1% of the number of terminated nodes in the WSN.

As one of the most widely investigated studies in wireless sensor networks (WSNs), multihop networking is increasingly developed and applied for achieving energy efficient communications and enhancing transmission reliability. To accurately and realistically analyze the performance metric (energy efficiency), firstly we provide a measurement of the energy dissipation for each state and establish a practical energy consumption model for a WSN. According to the analytical model of connectivity, Gaussian approximation approaches to experimental connection probability are expressed for optimization problem on energy efficiency. Moreover, for integrating experimental results with theories, we propose the methodology in multihop wireless sensor networks to maximize efficiency by nonlinear programming, considering energy consumptions and the total quantity of sensing data to base station. Furthermore, we present evaluations adapting to various wireless sensor networks quantitatively with respect to energy efficiency and network configuration, in view of connectivity, the length of data, maximum number of hops and total number of nodes. As the consequence, the realistic analysis can be used in practical applications, especially on self-organization sensor networks. The analysis also shows correlations between the efficiency and maximum number of hops, that is the multihop systems with several hops can accommodate enough devices in ordinary applications. In this paper, our contribution distinguished from others is that our model and analysis are extended from experiments. Therefore, the results of analysis and proposal can be conveniently applied to actual networks.

Razor Flip-Flop (FF) is a good combination for the dynamic voltage scaling (DVS) technique to achieve high energy efficiency. We previously proposed a RazorProtector scheme, which uses, under a very high IR-drop zone, a redundant data-path to provide a very fast recovery for a Razor-FF based processor. In this paper, we propose a dynamic method to adjust the redundancy level to fine-grained fit both the program behaviors and processor manufacturing variations so as to achieve an optimal power saving. We design an online turning method to adjust the redundancy level according to the most related parameters, ILP (Instruction Level Parallelism) and DCF (Delay Criticality Factor). Our simulation results show that under a workload suite with different behaviors, the adaptive redundancy can achieve better Energy Delay Product (EDP) reduction than any static controls. Compared to the traditional application of Razor-FF and DVS, our proposed dynamic control achieves an EDP reduction of 56% in average for the workloads we studied.

An orthogonal ray graph is an intersection graph of horizontal and vertical rays (closed half-lines) in the plane. Such a graph is 3-directional if every vertical ray has the same direction, and 2-directional if every vertical ray has the same direction and every horizontal ray has the same direction. We derive some structural properties of orthogonal ray graphs, and based on these properties, we introduce polynomial-time algorithms that solve the dominating set problem, the induced matching problem, and the strong edge coloring problem for these graphs. We show that for 2-directional orthogonal ray graphs, the dominating set problem can be solved in O(n2 log5 n) time, the weighted dominating set problem can be solved in O(n4 log n) time, and the number of dominating sets of a fixed size can be computed in O(n6 log n) time, where n is the number of vertices in the graph. We also show that for 2-directional orthogonal ray graphs, the weighted induced matching problem and the strong edge coloring problem can be solved in O(n2+m log n) time, where m is the number of edges in the graph. Moreover, we show that for 3-directional orthogonal ray graphs, the induced matching problem can be solved in O(m2) time, the weighted induced matching problem can be solved in O(m4) time, and the strong edge coloring problem can be solved in O(m3) time. We finally show that the weighted induced matching problem can be solved in O(m6) time for orthogonal ray graphs.

Single-thread performance has not improved much over the past few years, despite an ever increasing transistor budget. One of the reasons for this is that there is a speed gap between the processor and main memory, known as the memory wall. A promising method to overcome this memory wall is aggressive out-of-order execution by extensively enlarging the instruction window resources to exploit memory-level parallelism (MLP). However, simply enlarging the window resources lengthens the clock cycle time. Although pipelining the resources solves this problem, it in turn prevents instruction-level parallelism (ILP) from being exploited because issuing instructions requires multiple clock cycles. This paper proposed a dynamic scheme that adaptively resizes the instruction window based on the predicted available parallelism, either ILP or MLP. Specifically, if the scheme predicts that MLP is available during execution, the instruction window is enlarged and the window resources are pipelined, thereby exploiting MLP. Conversely, if the scheme predicts that less MLP is available, that is, ILP is exploitable for improved performance, the instruction window is shrunk and the window resources are de-pipelined, thereby exploiting ILP. Our evaluation results using the SPEC2006 benchmark programs show that the proposed scheme achieves nearly the best performance possible with fixed-size resources. On average, our scheme realizes a performance improvement of 21% over that of a conventional processor, with additional cost of only 6% of the area of the conventional processor core or 3% of that of the entire processor chip. The evaluation results also show 8% better energy efficiency in terms of 1/EDP (energy-delay product).

Cooperative communication has been proposed to improve the disadvantages of the multiple-input multiple-output (MIMO) technique without using extra multiple antennas. In an orthogonal frequency division multiple access (OFDMA) system, a cooperative communication that each user shares their allocated sub-channels instead of the MIMO system has been proposed to improve the throughput. But the cooperative communication has a problem as the decreased throughput because it is necessary that users send and receive the information to each other to improve reliability. In this letter, the modified cooperative transmission scheme is proposed to improve reliability in the fading channel, and it can solve the problem for BER performance that is dependent on the errors in the first phase that exchanges the information between both users during the first time.

This paper proposes an efficient two-scan labeling algorithm for binary hexagonal images. Unlike conventional labeling algorithms, which process pixels one by one in the first scan, our algorithm processes pixels two by two. We show that using our algorithm, we can check a smaller number of pixels. Experimental results demonstrated that our method is more efficient than the algorithm extended straightly from the corresponding labeling algorithm for rectangle binary images.

This paper shows a method to find a linear transformation that reduces the number of variables to represent a given incompletely specified index generation function. It first generates the difference matrix, and then finds a minimal set of variables using a covering table. Linear transformations are used to modify the covering table to produce a smaller solution. Reduction of the difference matrix is also considered.

We propose a synthesis method of nested loops into parallelized circuits by integrating the polyhedral optimization, which is a state-of-the-art technique in the field of software, into high-level synthesis. Our method constructs circuits equipped with multiple processing elements (PEs), using information generated by the polyhedral optimizing compiler. Since multiple PEs cannot concurrently access the off-chip RAM, a method for constructing on-chip buffers is also proposed. Our buffering method reduces the off-chip RAM access conflicts and further enables burst accesses and data reuses. In our experimental result, the buffered circuits generated by our method are 8.2 times on average and 26.5 times at maximum faster than the sequential non-buffered ones, when each of the parallelized circuits is configured with eight PEs.

Maximally flat digital differentiators (MFDDs) are widely used in many applications. By using MFDDs, we obtain the derivative of an input signal with high accuracy around their center frequency of flat property. Moreover, to avoid the influence of noise, it is desirable to attenuate the magnitude property of MFDDs expect for the vicinity of the center frequency. In this paper, we introduce a design method of linear phase FIR band-pass MFDDs with an arbitrary center frequency. The proposed transfer function for both of TYPE III and TYPE IV can be achieved as a closed form function using Jacobi polynomial. Furthermore, we can easily derive the weighting coefficients of the proposed MFDDs using recursive formula. Through some design examples, we confirm that the proposed method can adjust the center frequency arbitrarily and the band width having flat property.

Cognitive radio has been developed recently as a promising solution to tackle the spectrum related issues such as spectrum scarcity and spectrum underutilization. Cognitive spectrum assignment is necessary for allocating spectrum bands to secondary users in order to avoid conflicts among secondary users and maximize the total network performance under a given set of conditions. In most spectrum assignment schemes, throughput is considered as the main criterion for spectrum selection or spectrum assignment. In this paper, we propose a distortion-aware channel allocation scheme for multiple secondary users who compete for primary channels to transmit multimedia data. In the proposed scheme, idle spectrum bands are assigned to the multimedia secondary users that attain the highest video distortion reduction. The scheme is expected to mitigate the selfish behaviors of users in competing channels. The performance effectiveness of our proposed channel allocation scheme is demonstrated through simulation by comparing with a benchmark of two reference spectrum assignment schemes.

We propose a cyclic sleep control technique for backup resources in reconfigurable optical add/drop multiplexer (ROADM) systems to simultaneously achieve power savings and high-speed recovery from failures. Processes to check the reliability of backup resources, backup transponders and paths, are also provided in the control technique. The proposed technique uses sleep mode where backup transponders are powered down to minimize power for power savings. At least one of the backup transponders is always activated after self-checking using the loopback fiber connection in the ROADM and it becomes a shared backup for working transponders to enable high-speed recovery from failures. This activated backup transponder is powered down again after the next transponder is activated. These state transitions are cyclically applied to each backup transponder. This “cyclic” aspect of operation enables network operators to continuously monitor the reliability for all backup resources with the sleep mode. The activated backup transponders at both ends of the path are used in checking the reliability of backup paths. Therefore, all backup resources, both transponders and paths, can be regularly checked with the sleep mode to ensure data are stably forwarded. We estimated the power consumption with this technique under various conditions and found a trade-off between power reduction and the recovery capabilities from failures. We achieved more than 34% power saving of backup transponders maintaining the failure recovery time within 50ms in experiments. Furthermore, we confirmed the reliability of backup paths in experiments using backup transponders with the cyclic sleep control technique. These results indicated that the proposed control technique is promising in dramatically and reliably reducing the power consumption of backup resources.

This paper presents an oscillator-based true random number generator (TRNG) that dynamically unbiases 0/1 probability. The proposed TRNG automatically adjusts the duty cycle of a fast oscillator to 50%, and generates unbiased random numbers tolerating process variation and dynamic temperature fluctuation. A prototype chip of the proposed TRNG was fabricated with a 65nm CMOS process. Measurement results show that the developed duty cycle monitor obtained the probability of ‘1’ 4,100 times faster than the conventional output bit observation, or estimated the probability with 70 times higher accuracy. The proposed TRNG adjusted the probability of ‘1’ to within 50±0.07% in five chips in the temperature range of 0°C to 75°C. Consequently, the proposed TRNG passed the NIST and DIEHARD tests at 7.5Mbps with 6,670µm2 area.

Frequently interrupting someone who is busy will decrease his or her productivity. To minimize this risk, a number of interruptibility estimation methods based on PC activity such as typing or mouse clicks have been developed. However, these estimation methods do not take account of the effect of conversations in relation to the interruptibility of office workers engaged in intellectual activities such as scientific research. This study proposes an interruptibility estimation method that takes account of the conversation status. Two conversation indices, “In conversation” and “End of conversation” were used in a method that we developed based on our analysis of 50 hours worth of recorded activity. Experiments, using the conversation status as judged by the Wizard-of-OZ method, demonstrated that the estimation accuracy can be improved by the two indices. Furthermore, an automatic conversation status recognition system was developed to replace the Wizard-of-OZ procedure. The results of using it for interruptibility estimation suggest the effectiveness of the automatically recognized conversation status.

The Hierarchical Memory Machine (HMM) is a theoretical parallel computing model that captures the essence of computation on CUDA-enabled GPUs. The offline permutation is a task to copy numbers stored in an array a of size n to an array b of the same size along a permutation P given in advance. A conventional algorithm can complete the offline permutation by executing b[p[i]] ← a[i] for all i in parallel, where an array p stores the permutation P. We first present that the conventional algorithm runs $D_w(P)+2{nover w}+3L-3$ time units using n threads on the HMM with width w and latency L, where Dw(P) is the distribution of P. We next show that important regular permutations including transpose, shuffle, and bit-reversal permutations run $2{nover w}+2{nover kw}+2L-2$ time units on the HMM with k DMMs. We have implemented permutation algorithms for these regular permutations on GeForce GTX 680 GPU. The experimental results show that these algorithms run much faster than the conventional algorithm. We also present an offline permutation algorithm for any permutation running in $16{nover w}+16{nover kw}+16L-16$ time units on the HMM with k DMMs. Quite surprisingly, our offline permutation algorithm on the GPU achieves better performance than the conventional algorithm in random permutation, although the running time has a large constant factor. We can say that the experimental results provide a good example of GPU computation showing that a complicated but ingenious implementation with a larger constant factor in computing time can outperform a much simpler conventional algorithm.

Industrial applications such as automotive ones require a cheap communication mechanism to send out communication messages from node to node by their deadline time. This paper presents a design paradigm in which we optimize both assignment of a network node to a bus and slot multiplexing of a FlexRay network system under hard real-time constraints so that we can minimize the cost of wire harness for the FlexRay network system. We present a cost minimization problem as a non-linear model. We developed a network synthesis tool which was based on simulated annealing. Our experimental results show that our design paradigm achieved a 50.0% less cost than a previously proposed approach for a virtual cost model.

Subcarrier pairing (SP) and power allocation (PA) can improve the channel capacity of the OFDM multi-hop relay system. Due to limitations of processing complexity and energy consumption, symbol-level relaying, which only regenerates the constellation symbols at relay nodes, is more practical than code-level relaying that requires full decoding and encoding. By modeling multi-hop symbol-level relaying as a multi-staged parallel binary symmetric channel, this paper introduces a jointly optimal SP and PA scheme which maximizes the end to end data rate. Analytical arguments are given to reveal the structures and properties of the optimal solution, and simulation results are presented to illustrate and justify the optimality.

In this paper, a novel high-performance heuristic algorithm, named relay-race algorithm (RRA), which was proposed to approach a global optimal solution by exploring similar local optimal solutions more efficiently within shorter runtime for NP-hard problem is investigated. RRA includes three basic parts: rough search, focusing search and relay. The rough search is designed to get over small hills on the solution space and to approach a local optimal solution as fast as possible. The focusing search is designed to reach the local optimal solution as close as possible. The relay is to escape from the local optimal solution in only one step and to maintain search continuity simultaneously. As one of typical applications, multi-objective placement problem in physical design optimization is solved by the proposed RRA. In experiments, it is confirmed that the computational performance is considerably improved. RRA achieves overall Pareto improvement of two conflicting objectives: power consumption and maximal delay. RRA has its potential applications to improve the existing search methods for more hard problems.