In the channel measurement and characterization, selecting a suitable excitation signal for a specified scenario is the primary task. This letter describes several selecting criteria of the excitation signal for channel sounding. And then the popular types of probing signals are addressed and through simulations their accuracy performances are compared in time-varying channels. The conclusion is the Constant Amplitude Zero Auto-Correlation (CAZAC) sequence yields better results in time-varying scenarios.

Mirrored serpentine microstrip lines are proposed for a parallel high speed digital signaling to reduce the peak far-end crosstalk (FEXT) voltage. Mirrored serpentine microstrip lines consist of two serpentine microstrip lines, each one equal to a conventional normal serpentine microstrip line. However, one serpentine microstrip line of the mirrored serpentine microstrip lines is flipped in the length direction, and thus, two serpentine microstrip lines face each other. Time domain reflectometry measurements show that the peak FEXT voltage of the mirrored serpentine microstrip lines is reduced by 56.4% of that of conventional microstrip lines and 30.0% of that of conventional normal serpentine microstrip lines.

In this letter, a novel imaging method to reduce the hand shake blur of a cell phone camera without using frame memory is proposed. The method improves the captured image in real time through the use of two additional preview images whose parameters can be calculated in advance and stored in a look-up table. The method does not require frame memory, and thus it can significantly reduce the chip size. The scheme is suitable for integration into a low-cost image sensor of a cell phone camera.

New concept of CMOS nonvolatile memory is presented with demonstration of cell implementations. The memory cell, which is a comparator basically, makes use of comparator offset for storage quantity and the FN stress phenomena for cell programming. We also propose the stress-packet operation which is the relevant programming method to finely control the offset of the memory cell. The memory cell is multiple-time programmable while it is implemented in a standard CMOS process. We fabricated the memory cell arrays of the latch comparator and demonstrated that it is rewritten several times. We also investigated the reliability of cell data retention by monitoring programmed offsets for several months.

The operating speed scalability is demonstrated by using the forward body biasing method for a 1-V 0.18-µm CMOS true single-phase clocking (TSPC) dual-modulus prescaler. With the forward body bias voltage varying between 0 and 0.4 V, the maximum operating speed changes by about 40–50% and the maximum input sensitivity frequency changes by about 400%. This speed scalability is achieved with less than 0.5-dB phase noise degradation. This demonstration indicates that the forward body biasing method is instrumental to build a cost-saving power-efficient 1-V 0.18-µm CMOS radio for low-power WBAN and WSN applications.

While phrase-based statistical machine translation systems prefer to translate with longer phrases, this may cause errors in a free word order language, such as Japanese, in which the order of the arguments of the predicates is not solely determined by the predicates and the arguments can be placed quite freely in the text. In this paper, we propose to reorder the arguments but not the predicates in Japanese using a dependency structure as a kind of reordering. Instead of a single deterministically given permutation, we generate multiple reordered phrases for each sentence and translate them independently. Then we apply a re-ranking method using a discriminative approach by Ranking Support Vector Machines (SVM) to re-score the multiple reordered phrase translations. In our experiment with the travel domain corpus BTEC, we gain a 1.22% BLEU score improvement when only 1-best is used for re-ranking and 4.12% BLEU score improvement when n-best is used for Japanese-English translation.

In this paper, a low-complexity symbol-spaced turbo frequency domain equalization (FDE) algorithm based on Laurent decomposition is proposed for precoded binary continuous phase modulation (CPM) with modulation index h=1/2. At the transmitter, a precoder is utilized to eliminate the inherent memory of the CPM signal. At the receiver, a matched filter based on Laurent decomposition is utilized to make the detection symbol-spaced. As a result, the symbol-spaced iteration can be taken between the equalizer and the decoder directly without a CPM demodulator, and we derive a symbol-spaced soft interference cancellation frequency domain equalization (SSIC-FDE) algorithm for binary CPM with h=1/2. A new data block structure for FDE of partial response CPM is also presented. The computational complexity analysis and simulations show that this approach provides a complexity reduction and an impressive performance improvement over previously proposed turbo FDE algorithm for binary CPM with h=1/2 in multi-path fading channels.

A 315 MHz power-gated ultra low power transceiver for wireless sensor network is developed in 40 nm CMOS. The developed transceiver features an injection-locked frequency multiplier for carrier generation and a power-gated low noise amplifier with current second-reuse technique for receiver front-end. The injection-locked frequency multiplier implements frequency multiplication by edge-combining and thereby achieves 11 µW power consumption at 315 MHz. The proposed low noise amplifier achieves the lowest power consumption of 8.4 µW with 7.9 dB noise figure and 20.5 dB gain in state-of-the-art designs.

Conventional mechanisms proposed for enhancing quality of service (QoS) in 802.11 networks suffer from a lack of backward compatibility and fairness with and to legacy devices. In this paper, we present a cooperative mechanism, called TXOP (transmission opportunity) Exchange, that provides a legacy-neutral solution in which only stations (STAs) participating in TXOP Exchange cooperatively use their available bandwidth to satisfy their required throughputs, while other legacy devices continue to get the same throughput performance as before. Specifically, we discuss the implementation of TXOP Exchange in legacy 802.11 networks. We show that this mechanism can be realized with minor modifications to the RTS (request-to-send) frames of only the STAs participating in TXOP Exchange and without any replacement of legacy access points or STAs. We show an example of a proportional fair algorithm for fair and efficient MAC cooperation using a Nash bargaining solution (NBS). A simulation study using a realistic simulator verifies that the TXOP Exchange mechanism ensures legacy neutrality and fair and efficient cooperation even when a large number of legacy STAs coexist.

The market growths of smart-phones and thin clients have been significantly increasing communication traffic in mobile networks. To handle the increased traffic, network operators should consider how to leverage distributed wireless resources such as distributed spots of wireless local access networks. In this paper, we consider the system where multiple moving users share distributed wireless access points on their traveling routes between their start and goal points and formulate as an optimization problem. Then, we come up with three algorithms as a solution for the problem. The key idea here is 'longcut route instruction', in which users are instructed to choose a traveling route where less congested access points are available; even if the moving distance increases, the throughput for users in the system would improve. In this paper, we define the gain function. Moreover, we analyze the basic characteristics of the system using as a simple model as possible.

The performance of successive approximation register (SAR) analog-to-digital converter (ADC) is well balanced between power and speed compare to the conventional flash or pipeline architecture. The nonlinearities suffer from the CDAC mismatch and comparator offset degrades SAR ADC performance in terms of DNL and INL. An on chip histogram-based digitally assisted background calibration technique is proposed to cancel and relax the aforesaid nonlinearities. The calibration is performed using the input signal, watching the digital codes in the specified vicinity of the decision boundaries, and feeding back to control the compensation capacitor periodically. The calibration does not require special calibration signal or additional analog hardware which is simple and amenable to hardware or software implementations. A 9-bit SAR ADC with split CDAC has been implemented in a 65 nm CMOS technology and it achieves a peak SNDR of 50.81 dB and consumes 1.34 mW from a 1.2-V supply. +0.4/-0.4 LSB DNL and +0.5/-0.7 LSB INL are achieved after calibration. The ADC has input capacitance of 180 fF and occupies an area of 0.10.13 mm2.

This paper is about a new efficient method for the implementation of a Block Proportionate Normalized Least Mean Square (BPNLMS++) adaptive filter using the Fermat Number Transform (FNT) and its inverse (IFNT). These transforms present advantages compared to Fast Fourier Transform (FFT) and the inverse (IFFT). An efficient state space method for implementing the FNT over rectangular windows is used in the cases where there is a large overlap between the consecutive input signals. This is called Generalized Sliding Fermat Number Transform (GSFNT) and is useful for reducing the computational complexity of finite ring convolvers and correlators. In this contribution, we propose, as a first objective, an efficient state algorithm with the purpose of reducing the complexity of IFNT. This algorithm, called Inverse Generalized Sliding Fermat Number Transform (IGSFNT), uses the technique of Generalized Sliding associated to matricial calculation in the Galois Field. The second objective is to realize an implementation of the BPNLMS++ adaptive filter using GSFNT and IGSFNT, which can significantly reduce the computation complexity of the filter implantation on digital signal processors.

A power analysis attack is a well-known side-channel attack but the efficiency of the attack is frequently degraded by the existence of power components, irrelative to the encryption included in signals used for the attack. To enhance the performance of the power analysis attack, we propose a preprocessing method based on extracting encryption-related parts from the measured power signals. Experimental results show that the attacks with the preprocessed signals detect correct keys with much fewer signals, compared to the conventional power analysis attacks.

To improve the observability during the post-silicon validation, it is the key to select the limited trace signals effectively for the data acquisition. This paper proposes an automated trace signal selection algorithm, which uses the pruning-based strategy to reduce the exploration space. First, the restoration range is covered for each candidate signals. Second, the constraints are generated based on the conjunctive normal form (CNF) to avoid the conflict. Finally the candidates are selected through pruning-based enumeration. The experimental results indicate that the proposed algorithm can bring higher restoration ratios and is more effective compared to existing methods.

MISTY1 is a 64-bit block cipher that has provable security against differential and linear cryptanalysis. MISTY1 is one of the algorithms selected in the European NESSIE project, and it is recommended for Japanese e-Government ciphers by the CRYPTREC project. In this paper, we report on 12th order differentials in 3-round MISTY1 with FL functions and 44th order differentials in 4-round MISTY1 with FL functions both previously unknown. We also report that both data complexity and computational complexity of higher order differential attacks on 6-round MISTY1 with FL functions and 7-round MISTY1 with FL functions using the 46th order differential can be reduced to as much as 1/22 of the previous values by using multiple 44th order differentials simultaneously.

We present a new framework of the data-reusing (DR) adaptive algorithms by incorporating a constraint on noise, referred to as a noise constraint. The motivation behind this work is that the use of the statistical knowledge of the channel noise can contribute toward improving the convergence performance of an adaptive filter in identifying a noisy linear finite impulse response (FIR) channel. By incorporating the noise constraint into the cost function of the DR adaptive algorithms, the noise constrained DR (NC-DR) adaptive algorithms are derived. Experimental results clearly indicate their superior performance over the conventional DR ones.

We propose a fast and precise transient response and frequency characteristics simulation method for switching converters. This method uses a behavioral simulation tool without using a SPICE-like analog simulator. The nonlinear operation of the circuit is considered, and the nonlinear function is realized by defining the nonlinear formula based on the circuit operation and by applying feedback. To assess the accuracy and simulation time of the proposed simulation method, we designed current-mode buck and boost converters and fabricated them using a 0.18-µm high-voltage CMOS process. The comparison in the transient response and frequency characteristics among SPICE, the proposed program on a behavioral simulation tool which we named NSTVR (New Simulation Tool for Voltage Regulators) and experiments of fabricated IC chips showed good agreement, while NSTVR was more than 22 times faster in transient response and 85 times faster in frequency characteristics than SPICE in CPU time in a boost converter simulation.

As the Internet represents a key social infrastructure, its reliability is essential if we are to survive failures. Physical connectivity of networks is also essential as it characterizes reliability. There are collaboration structures, which are topological structures where two or more nodes are connected to a node, and collaboration structures are observed in transcriptional regulatory networks and the router-level topologies of ISPs. These collaboration structures are related to the reliability of networks. The main objective of this research is to find whether an increase in collaboration structures would improve reliability or not. We first categorize the topology into a three-level hierarchy for this purpose, i.e., top-level, middle-level, and bottom-level layers. We then calculate the reliability of networks. The results indicate that the reliability of most transcriptional regulatory networks is higher than that of one of router-level topologies. We then investigate the number of collaboration structures. It is apparent that there are much fewer collaboration structures between top-level nodes and middle-level nodes in router-level topologies. Finally, we confirm that the reliability of router-level topologies can be improved by rewiring to increase the collaboration structures between top-level and middle-level nodes.

In this paper, we propose a new method for the bias-dependent parameter extraction of a MOSFET, which covers DC to over 100 GHz. The DC MOSFET model provided by the chip foundry is assumed to be correct, and the core DC characteristics are designed to be asymptotically recovered at low frequencies. This is carried out by representing the corrections required at high frequencies using a bias-dependent Y matrix, assuming that a parasitic nonlinear two-port matrix (Y-wrapper) is connected in parallel with the core MOSFET. The Y-wrapper can also handle the nonreciprocity of the parasitic components, that is, the asymmetry of the Y matrix. The reliability of the Y-wrapper model is confirmed through the simulation and measurement of a one-stage common-source amplifier operating at several bias points. This paper will not discuss about non-linearity.

The lateral velocity is of importance in cases like target identification and traffic management. Conventional Doppler methods are not capable of measuring lateral velocities since they quantify only the radial component. Based on the spectrogram characteristic of laterally moving targets, an algorithm based on fractional Fourier transform has been studied in the signal processing literature. The algorithm searches the peak position of the transformation, and calculates the lateral velocity from the peak position. The performance analysis of this algorithm is carried out in this paper, which shows that this algorithm approaches Cramer-Rao bound with reasonable computational complexity. Simulations are conducted at last to compare the analytical performance and the experimental result.