The search functionality is under construction.
The search functionality is under construction.

Keyword Search Result

[Keyword] ATI(18690hit)

7321-7340hit(18690hit)

  • Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design

    Yuki ANDO  Seiya SHIBATA  Shinya HONDA  Hiroyuki TOMIYAMA  Hiroaki TAKADA  

     
    PAPER-High-Level Synthesis and System-Level Design

      Vol:
    E93-A No:12
      Page(s):
    2509-2516

    We present a hardware sharing method for design space exploration of multi-processor embedded systems. In our prior work, we had developed a system-level design tool named SystemBuilder which automatically synthesizes target implementation of a system from a functional description. In this work, we have extended SystemBuilder so that it can automatically synthesize an area-efficient implementation which shares a hardware module among different applications. With SystemBuilder, designers only need to enable an option in order to share a hardware module. The designers, therefore, can easily explore a design space including hardware sharing in short time. A case study shows the effectiveness of the hardware sharing on design space exploration.

  • Co-channel Interference Mitigation via Joint Frequency and Space Domains Base Station Cooperation for Multi-Cell OFDMA Systems

    Yizhen JIA  Xiaoming TAO  Youzheng WANG  Yukui PEI  Jianhua LU  

     
    PAPER

      Vol:
    E93-B No:12
      Page(s):
    3469-3479

    Base Station (BS) cooperation has been considered as a promising technology to mitigate co-channel interference (CCI), yielding great capacity improvement in cellular systems. In this paper, by combining frequency domain cooperation and space domain cooperation together, we design a new CCI mitigation scheme to maximize the total utility for a multi-cell OFDMA network. The scheme formulates the CCI mitigation problem as a mixture integer programming problem, which involves a joint user-set-oriented subcarrier assignment and power allocation. A computationally feasible algorithm based on Lagrange dual decomposition is derived to evaluate the optimal value of the problem. Moreover, a low-complexity suboptimal algorithm is also presented. Simulation results show that our scheme outperforms the counterparts incorporating BS cooperation in a single domain considerably, and the proposed low-complexity algorithm achieves near optimal performance.

  • A Censor-Based Cooperative Spectrum Sensing Scheme Using Fuzzy Logic for Cognitive Radio Sensor Networks

    Thuc KIEU-XUAN  Insoo KOO  

     
    LETTER

      Vol:
    E93-B No:12
      Page(s):
    3497-3500

    This letter proposes a novel censor-based scheme for cooperative spectrum sensing on Cognitive Radio Sensor Networks. A Takagi-Sugeno's fuzzy system is proposed to make the decision on the presence of the licensed user's signal based on the observed energy at each cognitive sensor node. The local spectrum sensing results are aggregated to make the final sensing decision at the fusion center after being censored to reduce transmission energy and reporting time. Simulation results show that significant improvement of the spectrum sensing accuracy, and saving energy as well as reporting time are achieved by our scheme.

  • An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation

    Young-Sang KIM  Yunjae SUH  Hong-June PARK  Jae-Yoon SIM  

     
    PAPER-Electronic Circuits

      Vol:
    E93-C No:12
      Page(s):
    1662-1669

    This paper presents a quantitative analysis and design methodology of resistor-based phase error averaging scheme for precise multiphase generation. Unlike the previously reported works stating that more averaging simply achieves better linearity, the proposed analysis leads to the existence of the optimum number of averaging contributions by including the effect of the signal transition time. The developed model shows a good agreement with a Monte-Carlo circuit simulation. A test PLL with a 32-phase two-dimensional ring VCO, implemented in a 0.18 µm CMOS, generates monotonous 32 phases with the best linearity performance, showing an INL of +0.27/-1.0 LSB and a DNL of +0.37/-0.27 LSB at 1.2 GHz, and an INL of +0.23/-1.57 LSB and a DNL of +0.44/-0.44 LSB at 1.6 GHz.

  • Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation

    Shinyu NINOMIYA  Masanori HASHIMOTO  

     
    PAPER-Device and Circuit Modeling and Analysis

      Vol:
    E93-A No:12
      Page(s):
    2441-2446

    Statistical timing analysis for manufacturing variability requires modeling of spatially-correlated variation. Common grid-based modeling for spatially-correlated variability involves a trade-off between accuracy and computational cost, especially for PCA (principal component analysis). This paper proposes to spatially interpolate variation coefficients for improving accuracy instead of fining spatial grids. Experimental results show that the spatial interpolation realizes a continuous expression of spatial correlation, and reduces the maximum error of timing estimates that originates from sparse spatial grids For attaining the same accuracy, the proposed interpolation reduced CPU time for PCA by 97.7% in a test case.

  • Phase Rotation for Constructing Uniform Frequency Spectrum in IFDMA Communication

    Takeo YAMASAKI  Osamu TAKYU  Koichi ADACHI  Yohtaro UMEDA  Masao NAKAGAWA  

     
    PAPER

      Vol:
    E93-A No:12
      Page(s):
    2672-2681

    In this paper, a scheme for constructing the flat frequency spectrum of interleaved frequency division multiple access (IFDMA) is proposed. Since IFDMA is one of the single carrier modulation schemes, the frequency spectrum components are fluctuated and depend on the information data sequence. Even if IFDMA modulation scheme makes frequency spectrum dispersive for obtaining frequency diversity gain, frequency diversity gain is reduced by the fluctuation of frequency spectrum. In addition, in decision directed channel estimation (DDCE), which achieves good channel estimation accuracy in fast fading environment, the accuracy of channel transfer function estimated at the significant attenuated frequency component is much degraded. In the proposed technique, a random phase sequence is multiplied to the information data sequence for constructing the flat frequency spectrum. As a result, the frequency diversity gain is enlarged and the accuracy of channel estimation by DDCE is improved. Furthermore, we consider the blind estimation technique for the random phase sequence selected by transmitter. We show the effects of the proposed scheme by computer simulation.

  • Channel Estimator Employing Narrowband Interference Detector of Wideband OFDM Receiver

    Naohiko IWAKIRI  Takehiko KOBAYASHI  

     
    PAPER

      Vol:
    E93-A No:12
      Page(s):
    2646-2653

    A multiband system can flexibly create spectral holes to avoid interference between different systems. When two systems within the same frequency band coexist, the multiband system must immediately detect the signals from all users to remove unwanted interference. The complication of creating spectral holes is to obtain an occupied frequency band and an angle-of-arrival of interfering system. These parameters must be measured at the receiver of multiband system and then fed back to the transmitter. This paper presents a channel estimator with an interference detector that is developed to implement and test it's functionality in a multiband system. The proposed estimator can precisely detect the parameters before demodulation, and quickly feed back the interfering system parameters to transmitter. The effective design and the detection error rate were evaluated via verification tests in an anechoic chamber and computer simulations. The results of the proposed technique show an ability of interference detection as well as channel estimation.

  • Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating

    Xin MAN  Takashi HORIYAMA  Shinji KIMURA  

     
    PAPER-Logic Synthesis, Test and Verification

      Vol:
    E93-A No:12
      Page(s):
    2472-2480

    Clock gating is the insertion of control signal for registers to switch off unnecessary clock signals selectively without violating the functional correctness of the original design so as to reduce the dynamic power consumption. Commercial EDA tools usually have a mechanism to generate clock gating logic based on the structural method where the control signals specified by designers are used, and the effectiveness of the clock gating depends on the specified control signals. In the research, we focus on the automatic clock gating logic generation and propose a method based on the candidate extraction and control signal selection. We formalize the control signal selection using linear formulae and devise an optimization method based on BDD. The method is effective for circuits with a lot of shared candidates by different registers. The method is applied to counter circuits to check the co-relation with power simulation results and a set of benchmark circuits. 19.1-71.9% power reduction has been found on counter circuitsafter layout and 2.3-18.0% cost reduction on benchmark circuits.

  • Iterative Throughput Calculation for Crosspoint Queued Switch

    Milutin RADONJIC  Igor RADUSINOVIC  Jelena CVOROVIC  Kenji YOSHIGOE  

     
    LETTER-Network System

      Vol:
    E93-B No:12
      Page(s):
    3635-3638

    In this letter, we propose a novel approximate method for throughput calculation of crossbar switch with buffers only in crosspoints, in the case of uniform traffic. It is an iterative method based on the balance equations that describe crosspoint buffer state. Due to some approximations, we derive very simple formulas suitable for matrix calculation. This method gives results very close to the results obtained by numerous simulations, especially for larger switch and long buffers.

  • Delay-Sensitive Retransmission Method Based on Network Coding in Wireless LANs

    Yosuke TANIGAWA  Jong-Ok KIM  Hideki TODE  

     
    PAPER

      Vol:
    E93-B No:12
      Page(s):
    3345-3353

    Recently, network coding (NC) has been popularly applied to wireless networks in order to improve scarce wireless capacity. In wireless LANs, NC can be applied to packet retransmission, and a base station can simultaneously retransmit multiple packets destined to different wireless stations by a single retransmission trial. On the other hand, NC creates additional packet delay at both base station and wireless stations, and hence, packet transfer delay may increase seriously. However, existing NC-based retransmission methods do not consider this additional delay explicitly. In addition, when the number of flows is small, NC exhibits less benefit because the chances of NC-based retransmission are highly reduced. Therefore, in this paper, we propose a novel NC-based retransmission method in order to improve packet transfer delay and jitter of received packets. Moreover, to achieve further improvement of delay, jitter and retransmission efficiency even when there exist a small number of traffic flows, we propose a retransmission method in which NC-based retransmission cooperates with the typical ARQ method. We overcome the disadvantage of NC-based retransmission by combining with ARQ cooperatively. Finally, we show the effectiveness of the proposed methods by extensive computer simulation.

  • Distributed Location Service with Spatial Awareness for Mobile Ad Hoc Networks

    Shyr-Kuen CHEN  Tay-Yu CHEN  Pi-Chung WANG  

     
    PAPER

      Vol:
    E93-B No:12
      Page(s):
    3400-3408

    A mobile ad-hoc network (MANET) consists of a collection of wireless mobile nodes without any fixed network infrastructure. Since the mobile nodes form a constantly changing topology, the design of efficient and scalable routing protocols is a fundamental challenge in MANETs. In the current literature, position-based routing protocols are regarded as having better scalability and lower control overhead than topology-based routing protocols. Since location services are the most critical part of position-based routing protocols, we present a multi-home-region scheme, Distributed Virtual Home Region with Spatial Awareness (DVHR-SA), to improve the performance of location service in this paper. Our scheme adaptively selects different update and query procedures according to the location of a source node. The simulation results show that DVHR-SA shortens the lengths of the update, query and reply paths. Our scheme also reduces the overall network message overhead. Therefore, DVHR-SA is considerably fast and stable.

  • Prioritized Aggregation for Compressed Video Streaming on mmWave WPAN Systems

    Zhou LAN  Chin Sean SUM  Junyi WANG  Hiroshi HARADA  Shuzo KATO  

     
    LETTER

      Vol:
    E93-A No:12
      Page(s):
    2704-2707

    This paper proposes a prioritized aggregation method that supports compressed video transmission on millimeter wave wireless personal area network (mmWave WPAN) systems. Frame aggregation is an effective means to improve system efficiency and throughput for wide band systems such as mmWave WPAN. It is required by the applications that the mmWave WPAN systems should provide Gbps or multiGbps transmission capability. The proposed scheme targets not only transmission efficiency but also support of compressed video transmission which currently is very popular. The proposal combines MAC layer aggregation with PHY layer skew modulation to facilitate the video transmission in a way that more important data is better protected. Simulation results show that the average peak signal to noise ratio (PSNR) performance is improved by 5 dB compared to conventional method, while the Gbps transmission requirement is fulfilled.

  • Optimal Configuration for Multiversion Real-Time Systems Using Slack Based Schedulability

    Sayuri TERADA  Toshimitsu USHIO  

     
    PAPER

      Vol:
    E93-A No:12
      Page(s):
    2709-2716

    In an embedded control system, control performances of each job depend on its latency and a control algorithm implemented in it. In order to adapt a job set to optimize control performances subject to schedulability, we design several types of control software for each job, which will be called versions, and select one version from them when the job is released. A real-time system where each job has several versions is called a multiversion real-time system. A benefit and a CPU utilization of a job depend on the versions. So, it is an important problem to select a version of each job so as to maximize the total benefit of the system subject to a schedulability condition. Such a problem will be called an optimal configuration problem. In this paper, we assume that each version is specified by the relative deadline, the execution time, and the benefit. We show that the optimal configuration problem is transformed to a maximum path length problem. We propose an optimal algorithm based on the forward dynamic programming. Moreover, we propose sub-optimal algorithms to reduce computation times. The efficiencies of the proposed algorithms are illustrated by simulations.

  • Analyzing the On-State Power Dissipation in Stepped-Output Diode-Clamped Multi-Level Inverter

    Ehsan ESFANDIARI  Norman Bin MARIUN  Mohammad Hamiruce MARHABAN  Azmi ZAKARIA  

     
    PAPER-Electronic Circuits

      Vol:
    E93-C No:12
      Page(s):
    1670-1678

    In renewable power generators, because of high initial cost and duty cycle of systems, efficiency parameter has an important place. For this reason, line frequency controlled multilevel inverters are one of most proper choices for renewable power converters. Among these, diode-clamped multilevel inverter structures are one of most important and best efficient inverters. In this paper, a simple diode-clamped equivalent circuit for exploring the efficiency under resistive loads is proposed, and based on this simple circuit, the on-state power dissipation in improved and original diode-clamped multilevel inverter under resistive loads is analyzed. Then, comparative efficiency equations are extracted for inverters that use metal oxide semiconductor field-effect transistors (MOSFETs) and other p-n junction as switches. These equations enable us to have a better idea of conducting power dissipation in diode-clamped and help us to choose appropriate switches for having a lower on-state power dissipation. Some cases are studied and in the end it is proven that the calculated efficiency under resistive load is a boundary for inductive load with the same impedance in diode-clamped inverter with p-n junction switches. This means that calculating the efficiency under resistive loads enables us to approximately predict efficiency under inductive loads.

  • Effect of Power Allocation Schemes on MIMO Two-Way Multi-Hop Network

    Jonghyun LEE  Gia Khanh TRAN  Kei SAKAGUCHI  Kiyomichi ARAKI  

     
    PAPER

      Vol:
    E93-B No:12
      Page(s):
    3362-3370

    Recently, wireless multi-hop network using MIMO two-way relaying technique has been attracted much attention owing to its high network efficiency. It is well known that the MIMO two-way multi-hop network (MTMN) can provide its maximum throughput in uniform topology of node location. However, in realistic environments with non-uniform topology, network capacity degrades severely due to unequal link quality. Furthermore, the end-to-end capacity also degrades at high SNR due to far (overreach) interference existing in multi-hop relay scenarios. In this paper, we focus on several power allocation schemes to improve the end-to-end capacity performance of MTMN with non-uniform topology and far interference. Three conventional power allocation schemes are reformulated and applied under the system model of MTMN. The first two are centralized methods, i.e., Eigenvector based Power Allocation (EPA) which employs linear algebra and Optimal Power Allocation (OPA) using convex optimization. The last one is Distributed Power Allocation (DPA) using game theory. It is found from numerical analyses that the power allocation schemes are effective for MTMN in terms of end-to-end capacity improvement, especially in non-uniform node arrangement and at high SNR.

  • Downlink Radio Resource Allocation for Coordinated Cellular OFDMA Networks

    Jingya LI  Xiaodong XU  Xin CHEN  Xiaofeng TAO  Hui ZHANG  Tommy SVENSSON  Carmen BOTELLA  

     
    PAPER

      Vol:
    E93-B No:12
      Page(s):
    3480-3488

    Base station coordination is considered as a promising technique to mitigate inter-cell interference and improve the cell-edge performance in cellular orthogonal frequency division multiple-access (OFDMA) networks. The problem to design an efficient radio resource allocation scheme for coordinated cellular OFDMA networks incorporating base station coordination has been only partially investigated. In this contribution, a novel radio resource allocation algorithm with universal frequency reuse is proposed to support base station coordinated transmission. Firstly, with the assumption of global coordination between all base station sectors in the network, a coordinated subchannel assignment algorithm is proposed. Then, by dividing the entire network into a number of disjoint coordinated clusters of base station sectors, a reduced-feedback algorithm for subchannel assignment is proposed for practical use. The utility function based on the user average throughput is used to balance the efficiency and fairness of wireless resource allocation. System level simulation results demonstrate that the reduced-feedback subchannel assignment algorithm significantly improves the cell-edge average throughput and the fairness index of users in the network, with acceptable degradation of cell-average performance.

  • Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation

    Takashi ENAMI  Shinyu NINOMIYA  Ken-ichi SHINKAI  Shinya ABE  Masanori HASHIMOTO  

     
    PAPER-Device and Circuit Modeling and Analysis

      Vol:
    E93-A No:12
      Page(s):
    2399-2408

    Clock driver suffers from delay variation due to manufacturing and environmental variabilities as well as combinational cells. The delay variation causes clock skew and jitter, and varies both setup and hold timing margins. This paper presents a timing verification method that takes into consideration delay variation inside a clock network due to both manufacturing variability and dynamic power supply noise. We also discuss that setup and hold slack computation inherently involves a structural correlation problem due to common paths, and demonstrate that assigning individual random variables to upstream clock drivers provides a notable accuracy improvement in clock skew estimation with limited increase in computational cost. We applied the proposed method to industrial designs in 90 nm process. Experimental results show that dynamic delay variation reduces setup slack by over 500 ps and hold slack by 16.4 ps in test cases.

  • Variation-Aware Task and Communication Scheduling in MPSoCs for Power-Yield Maximization

    Mahmoud MOMTAZPOUR  Maziar GOUDARZI  Esmaeil SANAEI  

     
    PAPER-High-Level Synthesis and System-Level Design

      Vol:
    E93-A No:12
      Page(s):
    2542-2550

    Parameter variations reveal themselves as different frequency and leakage powers per instances of the same MPSoC. By the increasing variation with technology scaling, worst-case-based scheduling algorithms result in either increasingly less optimal schedules or otherwise more lost yield. To address this problem, this paper introduces a variation-aware task and communication scheduling algorithm for multiprocessor system-on-chip (MPSoC). We consider both delay and leakage power variations during the process of finding the best schedule so that leakier processors are less utilized and can be more frequently put in sleep mode to reduce power. Our algorithm takes advantage of event tables to accelerate the statistical timing and power analysis. We use genetic algorithm to find the best schedule that maximizes power-yield under a performance-yield constraint. Experimental results on real world benchmarks show that our proposed algorithm achieves 16.6% power-yield improvement on average over deterministic worst-case-based scheduling.

  • Space Frequency Code for Cooperative Communications with both Timing Errors and Carrier Frequency Offsets

    Weile ZHANG  Huiming WANG  Qinye YIN  Wenjie WANG  

     
    LETTER

      Vol:
    E93-B No:12
      Page(s):
    3505-3508

    In this letter, we propose a simple distributed space-frequency code with both timing errors and multiple carrier frequency offsets (CFO) in asynchronous cooperative communications. By employing both the Alamouti coding approach and the transmit repetition diversity technique, full diversity gain can be achieved by the fast symbol-wise maximum likelihood (ML) decoding at the destination node. Analysis and simulations demonstrate the effectiveness of the proposed method.

  • Optimizing Position of Repeaters in Distributed MIMO Repeater System for Large Capacity

    Pham Thanh HIEP  Ryuji KOHNO  

     
    PAPER-Terrestrial Wireless Communication/Broadcasting Technologies

      Vol:
    E93-B No:12
      Page(s):
    3616-3623

    Multiple-input multiple-output (MIMO) repeater systems have been discussed in several published papers. When a repeater has only one antenna element, the propagation environment is called keyhole. In this kind of scenario the achievable channel capacity and link quality are decreased. Another limit is when the number of the antenna elements of a repeater is larger than that of a MIMO transceiver, the channel capacity cannot be increased. In this paper, in order to obtain an upper bound of the channel capacity, we express a propagation process of the distributed MIMO repeater system with amplify-and-forward method by the numerical formular, and optimize the position of each repeater.

7321-7340hit(18690hit)