In this paper, we propose a new class of two dimensional (2D) M-channel (M-ch) non-separable filter banks (FBs) based on cosine modulated filter banks (CMFBs) via a new diagonally modulation scheme. Until now, many researchers have proposed 2D non-separable CMFBs. Nevertheless, efficient direction-selective CMFBs have not been yet. Thanks to our new modulations with diagonal shifts, proposed CMFBs have several frequency supports including direction-selective ones which cannot be realized by conventional ones. In a simulation, we show design examples of proposed CMFBs and their various directional frequency supports.

In this paper, a new finger vein recognition method based on Gabor wavelet and Local Binary Pattern (GLBP) is proposed. In the new scheme, Gabor wavelet magnitude and Local Binary Pattern operator are combined, so the new feature vector has excellent stability. We introduce Block-based Linear Discriminant Analysis (BLDA) to reduce the dimensionality of the GLBP feature vector and enhance its discriminability at the same time. The results of an experiment show that the proposed approach has excellent performance compared to other competitive approaches in current literatures.

The mining problem over data streams has recently been attracting considerable attention thanks to the usefulness of data mining in various application fields of information science, and sequence data streams are so common in daily life. Therefore, a study on mining sequential patterns over sequence data streams can give valuable results for wide use in various application fields. This paper proposes a new framework for mining novel interesting sequential patterns over a sequence data stream and a mining method based on the framework. Assuming that a sequence with small time-intervals between its data elements is more valuable than others with large time-intervals, the novel interesting sequential pattern is defined and found by analyzing the time-intervals of data elements in a sequence as well as their orders. The proposed framework is capable of obtaining more interesting sequential patterns over sequence data streams whose data elements are highly correlated in terms of generation time.

This paper explores the problem of semantic enrichment of mathematical expressions. We formulate this task as the translation of mathematical expressions from presentation markup to content markup. We use MathML, an application of XML, to describe both the structure and content of mathematical notations. We apply a method based on statistical machine translation to extract translation rules automatically. This approach contrasts with previous research, which tends to rely on manually encoded rules. We also introduce segmentation rules used to segment mathematical expressions. Combining segmentation rules and translation rules strengthens the translation system and archives significant improvements over a prior rule-based system.

Small delay defects can cause serious issues such as very short lifetime in the recent VLSI devices. Delay measurement is useful to detect small delay defects in manufacturing testing. This paper presents a design for delay measurement to detect small delay defects on global routing resources, such as double, hex and long lines, in a Xilinx Virtex 4 based FPGA. This paper also shows a measurement method using the proposed design. The proposed measurement method is based on an existing one for SoC using delay value measurement circuit (DVMC). The proposed measurement modifies the construction of configurable logic blocks (CLBs) and utilizes an on-chip DVMC newly added. The number of configurations required by the proposed measurement is 60, which is comparable to that required by stuck-at fault testing for global routing resources in FPGAs. The area overhead is low for general FPGAs, in which the area of routing resources is much larger than that of the other elements such as CLBs. The area of every modified CLB is 7% larger than an original CLB, and the area of the on-chip DVMC is 22% as large as that of an original CLB. For recent FPGAs, we can estimate that the area overhead is approximately 2% or less of the FPGAs.

Nowadays, the trend of developing micro-processor with hundreds of cores brings a promising prospect for embedded systems. Realizing a high performance and low power many-core processor is becoming a primary technical challenge. Generally, three major issues required to be resolved includes: 1) realizing efficient massively parallel processing, 2) reducing dynamic power consumption, and 3) improving software productivity. To deal with these issues, we propose a solution to use many low-performance but small and very low-power cores to obtain very high performance, and develop a referential many-core architecture and a program development environment. This paper introduces a many-core architecture named SMYLEref and its prototype system with off-the-shelf FPGA evaluation boards. The initial evaluation results of several SPLASH2 benchmark programs conducted on our developed 128-core platform are also presented and discussed in this paper.

In the next generation mobile network, the demand for high data rate transmission will require an increase in the transmission power if the current mobile cellular network architecture is used. Multihop networks are considered to be a key solution to this problem. However, a new resource allocation algorithm is also required for the new network architecture. In this paper, we propose a resource allocation scheme for a parallel relay 2-hop OFDMA virtual cellular network (VCN) which can be applied in a multiuser environment. We evaluate, by computer simulation, the ergodic channel capacity of the VCN using the proposed algorithm, and compare the results with those of the conventional single hop network (SHN). In addition, we analyze the effect of the location of the relay wireless ports on the ergodic channel capacity of the VCN. We also study the degree of fairness of the VCN, using the proposed scheme, compared with that of the SHN. For low transmission power, the simulation results show: a) the VCN can provide a better ergodic channel capacity and a better degree of fairness than the SHN, b) the distance ratio for which the ergodic channel capacity of the VCN is maximal can be found in the interval 0.20.3, c) the ergodic channel capacity of the VCN remains better than that of the SHN as the number of users increases, and d) as the distance between the relay WPs and the base station increases, the channel capacity of VCN approaches that of the SHN.

This paper proposes a method for evaluating visual differences caused by decimation. In many applications it is important to evaluate visual differences of two different images. There exist many image assessment methods that utilize the model of the human visual system (HVS), such as the visual difference predictor (VDP) and the Sarnoff visual discrimination model. In this paper, we extend and elaborate on the conventional image assessment method for the purpose of evaluating the visual difference caused by the image decimation. Our method matches actual human evaluation more and requires less computational complexity than the conventional method.

In order to execute coherent Doppler processing in a high range-rate scenario, whether it is for detection, estimation or imaging, range walk embedded in target return should be compensated first. In case of a bistatic radar geometry where a transmitter, a receiver and a target can be all moving, the extent of range walk depends on their relative positions and velocities. This paper presents a coherent Doppler processing algorithm to achieve target detection and Doppler frequency estimation of a target under a bistatic radar geometry. This algorithm is based on the assumption that a target has constant Doppler frequency during a coherent processing interval (CPI). Thus, we first show under what condition the assumption could be valid. We next develop an algorithm, along with its implementation procedures where the region of range walk, called a window, is manipulated. Finally, the performance of a proposed algorithm is examined through simulations.

This paper proposes a novel high-temperature superconducting dual-band bandpass filter (HTS-DBPF), that employs a broadside coupling structure, in which quarter-wavelength resonators are formed on opposite sides of each substrate. This structure provides a dual-band operation of the BPF and flexibility, in the sense of having a wide range in selecting two center passband frequencies of the HTS-DBPF. This paper employs the ratio of the lower and higher center passband frequencies, α, as a criterion for evaluating the flexibility. The obtained α ranges are from 1 to 4.7, which are the widest for DBPFs for mobile communications applications, to the best knowledge of the authors. This paper presents a 2.4-/2.9-GHz band HTS-DBPF, as an experimental example, using a YBCO film deposited on an MgO substrate. The measured frequency responses of the HTS-DBPF agree with the electromagnetic simulated results. Measurement and simulation results confirm that the proposed filter architecture is effective in configuring a DBPF that can set each center passband frequency widely.

Petri nets are a kind of formal language that are widely applied in concurrent systems associated with resource allocation due to their abilities of the natural description on resource allocation and the precise characterization on deadlock. Weighted System of Simple Sequential Processes with Resources (WS3PR) is an important subclass of Petri nets that can model many resource allocation systems in which 1) multiple processes may run in parallel and 2) each execution step of each process may use multiple units from a single resource type but cannot use multiple resource types. We first prove that the liveness problem of WS3PR is co-NP-hard on the basis of the partition problem. Furthermore, we present a necessary and sufficient condition for the liveness of WS3PR based on two new concepts called Structurally Circular Wait (SCW) and Blocking Marking (BM), i.e., a WS3PR is live iff each SCW has no BM. A sufficient condition is also proposed to guarantee that an SCW has no BM. Additionally, we show some advantages of using SCW to analyze the deadlock problem compared to other siphon-based ones, and discuss the relation between SCW and siphon. These results are valuable to the further research on the deadlock prevention or avoidance for WS3PR.

A complete 4-level pulse amplitude modulation (4-PAM) serial link transceiver including a wide frequency range clock generator and clock data recovery (CDR) is proposed in this paper. A dual-loop architecture, consisting of a frequency locked loop (FLL) and a phase locked loop (PLL), is employed for the wide frequency range clocks. The generated clocks from the FLL (clock generator) and the PLL (CDR) are utilized for a transmitter clock and a receiver clock, respectively. Both FLL and PLL employ the identical voltage controlled oscillators consisting of ring-type delay-cells. To improve the frequency tuning range of the VCO, deep triode PMOS loads are utilized for each delay-cell, since the turn-on resistance of the deep triode PMOS varies substantially by the gate-voltage. As a result, fabricated in a 0.13-µm CMOS process, the proposed 4-PAM transceiver operates from 1.5 Gb/s to 9.7 Gb/s with a bit error rate of 10-12. At the maximum data-rate, the entire power dissipation of the transceiver is 254 mW, and the measured jitter of the recovered clock is 1.61 psrms.

Comparable Corpora are valuable resources for many NLP applications, and extensive research has been done on information mining based on comparable corpora in recent years. While there are not enough large-scale available public comparable corpora at present, this paper presents a bi-directional CLIR-based method for creating comparable corpora from two independent news collections in different languages. The original Chinese document collections and English documents collections are crawled from XinHuaNet respectively and formatted in a consistent manner. For each document from the two collections, the best query keywords are extracted to represent the essential content of the document, and then the keywords are translated into the language of the other collection. The translated queries are run against the collection in the same language to pick up the candidate documents in the other language and candidates are aligned based on their publication dates and the similarity scores. Results show that our approach significantly outperforms previous approaches to the construction of Chinese-English comparable corpora.

Data encryption and decryption are common operations in network-based application programs that must offer security. In order to keep pace with the high data input rate of network-based applications such as the multimedia data streaming, real-time processing of the data encryption/decryption is crucial. In this paper, we propose a new parallelization approach to improve the throughput performance for the de-facto standard data encryption and decryption algorithm, AES-CTR (Counter mode of AES). The new approach extends the size of the block encrypted at one time across the unit block boundaries, thus effectively encrypting multiple unit blocks at the same time. This reduces the associated parallelization overheads such as the number of procedure calls, the scheduling and the synchronizations compared with previous approaches. Therefore, this leads to significant throughput performance improvements on a computing platform with a general-purpose multi-core processor and a Graphic Processing Unit (GPU).

In this paper, a stochastic asymptotic stabilization method is proposed for deterministic input-affine control systems, which are randomized by including Gaussian white noises in control inputs. The sufficient condition is derived for the diffusion coefficients so that there exist stochastic control Lyapunov functions for the systems. To illustrate the usefulness of the sufficient condition, the authors propose the stochastic continuous feedback law, which makes the origin of the Brockett integrator become globally asymptotically stable in probability.

For source camera identification, we propose a method to reconstruct the sensor pattern noise map from a size-reduced query image by minimizing an objective function derived from the observation model. Our method can be applied to multiple queries, and can thus be further improved. Experiments demonstrate the superiority of the proposed method over conventional interpolation-based magnification algorithms.

A method of calculating the top event probability of a fault tree, where dynamic gates and repeated events are included and the occurrences of basic events follow nonexponential distributions, is proposed. The method is on the basis of the Bayesian network formulation for a DFT proposed by Yuge and Yanagi [1]. The formulation had a difficulty in calculating a sequence probability if components have nonexponential failure distributions. We propose an alternative method to obtain the sequence probability in this paper. First, a method in the case of the Erlang distribution is discussed. Then, Tijms's fitting procedure is applied to deal with a general distribution. The procedure gives a mixture of two Erlang distributions as an approximate distribution for a general distribution given the mean and standard deviation. A numerical example shows that our method works well for complex systems.

This study investigated the test-retest reliability and the criterion-related validity of the Implicit Association Test (IAT [1]) that was developed for measuring shyness among Japanese people. The IAT has been used to measure implicit stereotypes, as well as self-concepts, such as implicit shyness and implicit self-esteem. We administered the shyness IAT and the self-esteem IAT to participants (N = 59) on two occasions over a one-week interval (Time 1 and Time 2) and examined the test-retest reliability by correlating shyness IATs between the two time points. We also assessed the criterion-related validity by calculating the correlation between implicit shyness and implicit self-esteem. The results indicated a sufficient positive correlation coefficient between the scores of implicit shyness over the one-week interval (r = .67, p < .01). Moreover, a strong negative correlation coefficient was indicated between implicit shyness and implicit self-esteem (r = -.72, p < .01). These results confirmed the test-retest reliability and the criterion-related validity of the Japanese version of the shyness IAT, which is indicative of the validity of the test for assessing implicit shyness.

A procedural terrain generation method is presented in this paper. It uses a user-drawn sketch map, which is a raster image with lines and polygons painted by different colors to represent sketches of different terrain features, as input to control the placement of terrain features. Some simple parameters which can be easily understood and adjusted by users are used to control the generation process. To further automatically generate terrains, a mechanism that automatically generates sketches is also put forward. The method is implemented in a PC, and experiments show that terrains are generated efficiently. This method provides users a controllable way to generate terrains.

Managing the configurations of complex systems consisting of various components requires the combined efforts by multiple domain experts. These experts have extensive knowledge about different components in the system they need to manage but little understanding of the issues outside their individual areas of expertise. As a result, the configuration constraints, changes, and procedures specified by those involved in the management of a complex system are often interrelated with one another without being noticed, and their integration into a coherent procedure for configuration represents a major challenge. The method of synthesizing the configuration procedure introduced in this paper addresses this challenge using a combination of formal specification and model finding techniques. We express the knowledge on system management with this method, which is provided by domain experts as first-order logic formulas in the Alloy specification language, and combine it with system-configuration information and the resulting specification. We then employ the Alloy Analyzer to find a system model that satisfies all the formulas in this specification. The model obtained corresponds to a procedure for system configurations that satisfies all expert-specified constraints. In order to reduce the resources needed in the procedure synthesis, we reduce the length of procedures to be synthesized by defining and using intermediate goal states to divide operation procedures into shorter steps. Finally, we evaluate our method through a case study on a procedure to consolidate virtual machines.