In this paper, we introduce generalized feed-forward shift registers (GF2SR) to apply them to secure and testable scan design. Previously, we introduced SR-equivalents and SR-quasi-equivalents which can be used in secure and testable scan design, and showed that inversion-inserted linear feed-forward shift registers (I2LF2SR) are useful circuits for the secure and testable scan design. GF2SR is an extension of I2LF2SR and the class is much wider than that of I2LF2SR. Since the cardinality of the class of GF2SR is much larger than that of I2LF2SR, the security level of scan design with GF2SR is much higher than that of I2LF2SR. We consider how to control/observe GF2SR to guarantee easy scan-in/out operations, i.e., state-justification and state-identification problems are considered. Both scan-in and scan-out operations can be overlapped in the same way as the conventional scan testing, and hence the test sequence for the proposed scan design is of the same length as the conventional scan design. A program called WAGSR (Web Application for Generalized feed-forward Shift Registers) is presented to solve those problems.

Cardinality estimation schemes of Radio Frequency IDentification (RFID) tags using Framed Slotted ALOHA (FSA) based protocol are studied in this paper. Not as same as previous estimation schemes, we consider tag cardinality estimation problem under not only detection errors but also capture effect, where a tag's IDentity (ID) might not be detected even in a singleton slot, while it might be identified even in a collision slot due to the fading of wireless channels. Maximum Likelihood (ML) approach is utilized for the estimation of the detection error probability, the capture effect probability, and the tag cardinality. The performance of the proposed method is evaluated under different system parameters via computer simulations to show the method's effectiveness comparing to other conventional approaches.

In this letter, we present a joint blind adaptive scheme to suppress inter-block interference and estimate a carrier frequency offset (CFO) in downlink OFDMA systems. The proposed scheme is a combination of a channel shortening method and a CFO estimator, both based on the carrier nulling criterion. Simulation results demonstrate the effectiveness of the proposed scheme.

In this paper, a high performance current latch sense amplifier (CLSA) with vertical MOSFET is proposed, and its performances are investigated. The proposed CLSA with the vertical MOSFET realizes a 11% faster sensing time with about 3% smaller current consumption relative to the conventional CLSA with the planar MOSFET. Moreover, the proposed CLSA with the vertical MOSFET achieves an 1.11 dB increased voltage gain G(f) relative to the conventional CLSA with the planar MOSFET. Furthermore, the proposed CLSA realizes up to about 1.7% larger yield than the conventional CLSA, and its circuit area is 42% smaller than the conventional CLSA.

First, this paper derives the prefix sum-of-products expression (PreSOP) and the number of products in a PreSOP for an interval function. Second, it derives Ψ(n,τp), the number of n-variable interval functions that can be represented with τp products. Finally, it shows that more than 99.9% of the n-variable interval functions can be represented with ⌈ n - 1 ⌉ products, when n is sufficiently large. These results are useful for a fast PreSOP generator and for estimating the size of ternary content addressable memories (TCAMs) for packet classification.

With the rapid expansion of vector data model application to digital content such as drawings and digital maps, the security and retrieval for vector data models have become an issue. In this paper, we present a vector data-hashing algorithm for the authentication, copy protection, and indexing of vector data models that are composed of a number of layers in CAD family formats. The proposed hashing algorithm groups polylines in a vector data model and generates group coefficients by the curvatures of the first and second type of polylines. Subsequently, we calculate the feature coefficients by projecting the group coefficients onto a random pattern, and finally generate the binary hash from binarization of the feature coefficients. Based on experimental results using a number of drawings and digital maps, we verified the robustness of the proposed hashing algorithm against various attacks and the uniqueness and security of the random key.

In forthcoming sensor networks, a multitude of sensor nodes deployed over a large geographical area for monitoring traffic, climate, etc. are expected to become an inevitable infrastructure. Clustering algorithms play an important role in aggregating a large volume of data that are produced continuously by the huge number of sensor nodes. In such networks, equal-sized multi-hop clusters which include an equal number of nodes are useful for efficiency and resiliency. In addition, scalability is important in such large-scale networks. In this paper, we mathematically design a decentralized equal-sized clustering algorithm using a partial differential equation based on the Fourier transform technique, and then design its protocol by discretizing the equation. We evaluated through simulations the equality of cluster sizes and the resiliency against packet loss and node failure in two-dimensional perturbed grid topologies.

We investigated the effects of chemical treatments for removing native oxide layers on InAlN surfaces by X-ray photoelectron spectroscopy (XPS). The untreated surface of the air exposed InAlN layer was covered with the native oxide layer mainly composed of hydroxides. Hydrochloric acid treatment and ammonium hydroxide treatment were not efficient for removing the native oxide layer even after immersion for 15 min, while hydrofluoric acid (HF) treatment led to a removal in a short treatment time of 1 min. After the HF treatment, the surface was prevented from reoxidation in air for 1 h. We also found that the 5-min buffered HF treatment had almost the same effect as the 1-min HF treatment. Finally, an attempt was made to apply the HF-based treatment to the metal-InAlN contact to confirm the XPS results.

We have fabricated MOS capacitors with a hybrid floating gate (FG) consisting of Ni silicide nanodots (NiSi-NDs) and silicon-quantum-dots (Si-QDs) and studied electron transfer characteristics in the hybrid FG structures induced by the irradiation of 1310 nm light. The flat-band voltage shift due to the charging of the hybrid FG under light irradiation was lower than that in the dark. The observed optical response can be attributed to the shift of the charge centroid in the hybrid FG caused by the photoexcitation of electrons in NiSi-NDs and their transfer to Si-QDs. The photoexcited electron transfer from the NiSi-NDs to the Si-QDs in response to pulsed gate voltages was also evaluated from the increase in transient current caused by the light irradiation. The amount of transferred charge is likely to increase in proportion to pulse gate voltage.

As means to control interface reactions between HfO2 and Ge(100), chemical vapor deposition (CVD) of ultrathin Ta-rich oxide using Tri (tert-butoxy) (tert-butylimido) tantalum (Ta-TTT) on chemically-cleaned Ge(100) has been conducted prior to atomic-layer controlled CVD of HfO2 using tetrakis (ethylmethylamino) hafnium (TEMA-Hf) and O3. The XPS analysis of chemical bonding features of the samples after the post deposition N2 annealing at 300 confirms the formation of TaGexOy and the suppression of the interfacial GeO2 layer growth. The energy band structure of HfO2/TaGexOy/Ge was determined by the combination of the energy bandgaps of HfO2 and TaGexOy measured from energy loss signals of O 1s photoelectrons and from optical absorption spectra and the valence band offsets at each interface measured from valence band spectra. From the capacitance-voltage (C-V) curves of Pt-gate MIS capacitors with different HfO2 thicknesses, the thickness reduction of TaGexOy with a relative dielectric constant of 9 is a key to obtain an equivalent SiO2 thickness (EOT) below 0.7 nm.

As technology scales to 45 nm and below, the reliability of VLSI declines due to small delay defects, which are hard to detect by functional clock frequency. To detect small delay defects, a method which measures the delay time of path in circuit under test (CUT) was proposed. However, because a large number of FFs exist in recent VLSI, the probability that the resistive defect occurs in the FFs is increased. A test method measuring path delay time including the transmission time of FFs is necessary. However, the path measured by the conventional on-chip path delay time measurement method does not include a part of a master latch. Thus, testing using the conventional measurement method cannot detect defects occurring on the part. This paper proposes an improved on-chip path delay time measurement method. Test coverage is improved by measuring the path delay time including transmission time of a master latch. The proposed method uses a duty-cycle-modified clock signal. Evaluation results show that, the proposed method improves test coverage 5.2511.28% with the same area overhead as the conventional method.

Optical buffering has been one of the major technical challenges in realizing optical packet switching routers and interconnects. We demonstrate a compact optical buffer module, comprising an InP 18 phased-array switch and a silica-based delay line circuit. The integrated delay line circuit is fabricated on the silica-based planar-lightwave circuit (PLC) platform, and has the ladder architecture for reducing the size. In addition, variable optical couplers are integrated to achieve effective power equalization. Tunable and uniform buffering of up to 21 ns is obtained with 3-ns temporal resolution.

Searching for the shortest paths from a query point to several target points on a road network is an essential operation for several types of queries in location-based services. This search can be performed using Dijkstra's algorithm. Although the A* algorithm is faster than Dijkstra's algorithm for finding the shortest path from a query point to a target point, the A* algorithm is not so fast to find all paths between each point and the query point when several target points are given. In this case, the search areas on road network overlap for each search, and the total number of operations at each node is increased, especially when the number of query points increases. In the present paper, we propose the single-source multi-target A* (SSMTA*) algorithm, which is a multi-target version of the A* algorithm. The SSMTA* algorithm guarantees at most one operation for each road network node, and the searched area on road network is smaller than that of Dijkstra's algorithm. Deng et al. proposed the LBC approach with the same objective. However, several heaps are used to manage the search area on the road network and the contents in each heap must always be kept the same in their method. This operation requires much processing time. Since the proposed method uses only one heap, such content synchronization is not necessary. The present paper demonstrates through empirical evaluations that the proposed method outperforms other similar methods.

Developing a complex network accelerator like an IPsec processor is a great challenge. To this end, we propose a Network Virtual Platform ( NetVP ) that consists of one or more virtual host (vHOST) modules and virtual local area network (vLAN) modules to support electronic system level (ESL) top-down design flow as well as provide the on-line verification throughout the entire development process. The on-line verification capability of NetVP enables the designed target to communicate with a real network for system validation. For ESL top-down design flow, we also propose untimed and timed interfaces to support hardware/software co-simulation. In addition, the NetVP can be used in conjunction with any ESL development platform through the untimed/timed interface. System development that uses this NetVP is efficient and flexible since it allows the designer to explore design spaces such as the network bandwidth and system architecture easily. The NetVP can also be applied to the development of other kinds of network accelerators.

The noise in digital images acquired by image sensors has complex characteristics due to the variety of noise sources. However, most noise reduction methods assume that an image has additive white Gaussian noise (AWGN) with a constant standard deviation, and thus such methods are not effective for use with image signal processors (ISPs). To efficiently reduce the noise in an ISP, we estimate a unified noise model for an image sensor that can handle shot noise, dark-current noise, and fixed-pattern noise (FPN) together, and then we adaptively reduce the image noise using an adaptive Smallest Univalue Segment Assimilating Nucleus ( SUSAN ) filter based on the unified noise model. Since our noise model is affected only by image sensor gain, the parameters for our noise model do not need to be re-configured depending on the contents of image. Therefore, the proposed noise model is suitable for use in an ISP. Our experimental results indicate that the proposed method reduces image sensor noise efficiently.

In this letter, we present an efficient method for high quality surface reconstruction from simulation data of smoothed particles hydrodynamics (SPH). For computational efficiency, instead of computing scalar field in overall particle sets, we only construct scalar field around fluid surfaces. Furthermore, an adaptive scalar field model is proposed, which adaptively adjusts the smoothing length of ellipsoidal kernel by a constraint-correction rule. Then the isosurfaces are extracted from the scalar field data. The proposed method can not only effectively preserve fluid details, such as splashes, droplets and surface wave phenomena, but also save computational costs. The experimental results show that our method can reconstruct the realistic fluid surfaces with different particle sets.

The wideband noise controlling performance of the delayless subband adaptive filtering technique is affected by the group delay and in-band aliasing distortion of analysis filter banks. A method of recursive second-order cone programming is proposed to design the uniform DFT modulated analysis filter banks, with a small in-band aliasing error and low group delay. Simulation results show that the noise controlling performance is improved with small residual noise power spectra, a high noise attenuation level and fast convergence rate.

A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (Ion) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) for the fixed n-layer length (Ln-layer). The simulation results have been analyzed in terms of on- and off-current (Ion and Ioff), subthreshold swing (SS), and RF performances.

Training one-class support vector machines (one-class SVMs) involves solving a quadratic programming (QP) problem. By increasing the number of training samples, solving this QP problem becomes intractable. In this paper, we describe a modified Pegasos algorithm for fast training of one-class SVMs. We show that this algorithm is much faster than the standard one-class SVM without loss of performance in the case of linear kernel.

A predictive spatio-temporal interval join finds all pairs of moving objects satisfying a join condition on future time interval and space. In this paper, we propose a method called PTJoin. PTJoin partitions the inner index into small sub-trees and performs the join process for each sub-tree to reduce the number of disk page accesses for each window search. Furthermore, to reduce the number of pages accessed by consecutive window searches, we partition the index so that overlapping index pages do not belong to the same partition. Our experiments show that PTJoin reduces the number of page accesses by up to an order of magnitude compared to Interval_STJoin [9], which is the state-of-the-art solution, when the buffer size is small.