This paper surveys the results of various studies on 3-D image coding. Themes are focused on efficient compression and display-independent representation of 3-D images. Most of the works on 3-D image coding have been concentrated on the compression methods tuned for each of the 3-D image formats (stereo pairs, multi-view images, volumetric images, holograms and so on). For the compression of stereo images, several techniques concerned with the concept of disparity compensation have been developed. For the compression of multi-view images, the concepts of disparity compensation and epipolar plane image (EPI) are the efficient ways of exploiting redundancies between multiple views. These techniques, however, heavily depend on the limited camera configurations. In order to consider many other multi-view configurations and other types of 3-D images comprehensively, more general platform for the 3-D image representation is introduced, aiming to outgrow the framework of 3-D "image" communication and to open up a novel field of technology, which should be called the "spatial" communication. Especially, the light ray based method has a wide range of application, including efficient transmission of the physical world, as well as integration of the virtual and physical worlds.

There are two dynamics issues in vision chips: (i) The temporal dynamics issue due to the parasitic capacitors in a CMOS chip, and (ii) the spatial dynamics issue due to the regular array of processing elements in a chip. These issues are discussed in [1]-[3] for the resistor network with only associated parasitic capacitances. However, in this paper we consider also parasitic inductances as well as parasitic capacitances for a more precise network dynamics model. We show that in some cases the temporal stability condition for the network with parasitic inductances and capacitances is equivalent to that for the network with only parasitic capacitances, but in general they are not equivalent. We also show that the spatial stability conditions are equivalent in both cases.

Human faces convey various information, including that is specific to each individual person and that is part of mutual communication among persons. Information exhibited by a "face" is what is called "non-verbal information" and usually verbal media cannot easily describe such information appropriately. Recently, detailed studies on the processing of face images by a computer have been carried out in the engineering field for applications to communication media and human computer interaction as well as automatic identification of human faces. Two main technical topics are the recognition of human faces and the synthesis of face images. The objective of the former is to enable a computer to detect and identify users and further to recognize their facial expressions, while that of the latter is to provide a natural and impressive user interface on a computer in the form of a "face. " These studies have also been found to be useful in various non-engineering fields related to a face, such as psychology, anthropology, cosmetology and dentistry. Most of the studies in these different fields have been carried out independently up to now, although all of them deal with a "face. " Now in virtue of the progress in the above engineering technologies a common study tools and databases for facial information have become available. On the basis of these backgrounds, this paper surveys recent research trends in the processing of face images by a computer and its typical applications. Firstly, the various characteristics of faces are considered. Secondly, recent research activities in the recognition and synthesis of face images are outlined. Thirdly, the applications of digital processing methods of facial information are discussed from several standpoints: intelligent image coding, media handling, human computer interaction, caricature, facial impression, psychological and medical applications. The common tools and databases used in the studies of processing of facial information and some related topics are also described.

The Conjugate Residual method, one of the iterative methods for solving linear systems, is applied to the problems with a dense coefficient matrix on distributed memory parallel computers. Based on an assumption on the computation and communication times of the proposed algorithm for parallel computers, it is shown that the optimal number of processing elements is proportional to the problem size N. The validity of the prediction is confirmed through numerical experiments on Hitachi SR2201.

In this article we present a survey of medical image processing with the stress on applications of image generation and pattern recognition / understanding to computer aided diagnosis (CAD) and surgery (CAS). First, topics and fields of research in medical image processing are summarized. Second the importance of the 3D image processing and the use of virtualized human body (VHB) is pointed out. Thirdly the visualization and the observation methods of the VHB are introduced. In the forth section the virtualized endoscope system is presented from the viewpoint of the observation of the VHB with the moving viewpoints. The fifth topic is the use of VHB with deformation such as the simulation of surgical operation, intra-operative aids and image overlay. In the seventh section several topics on image processing methodologies are introduced including model generation, registration, segmentation, rendering and the use of knowledge processing.

Recently, we proposed a low power consumption FIR switched-capacitor filter constructed with capacitors having capacitances in proportion to square roots of transfer function coefficient values. It is referred to as an FIR semi-parallel cyclic type (SPCT) filter. In this paper, we present IIR SPCT filter. It needs only a single operational amplifier, hence being low power consumption. The IIR SPCT filter has smaller total capacitance than one of the IIR parallel cyclic type (PCT) filter and better high frequency response than one of the IIR transfer function coefficient ratio (TCR) filter. As a whole, the IIR SPCT filter has middle performance of the IIR PCT and TCR filters for the total capacitance, the number of types of clock pulses, and high frequency response.

Phase performance in a fiber optic temperature sensor using a mode-division multiplex is studied. The phase shift due to the temperature change of a multimode graded-index optical fiber is analyzed. The intensity fluctuation by the interference of two modes is estimated in computer simulation.

The star graph has been known as an attractive alternative to the hypercube multiprocessor. Like the hypercube, the star graph possesses the properties of symmetry, partionability and fault tolerance, but with a smaller diameter and degree than those of the hypercube. When tasks arrive at the star graph, the tasks should be assigned appropriate free processors before execution. A new model, called Star graph (Sg)-lattice, is proposed to model the construction and free configuration of the star graph. Based on this model, the Sg-lattice scheme can fully recognize the substars. Finally, mathematical analyses and simulation results show that the Sg-lattice scheme outperforms the previous work in the storage and time complexities and the average allocation time.

In this paper, the generalized learning vector quantization (GLVQ) algorithm is applied to design a hand-written Chinese character recognition system. The system proposed herein consists of two modules, feature transformation and recognizer. The feature transformation module is designed to extract discriminative features to enhance the recognition performance. The initial feature transformation matrix is obtained by using Fisher's linear discriminant (FLD) function. A template matching with minimum distance criterion recognizer is used and each character is represented by one reference template. These reference templates and the elements of the feature transformation matrix are trained by using the generalized learning vector quantization algorithm. In the experiments, 540100 (5401 100) hand-written Chinese character samples are used to build the recognition system and the other 540100 (5401 100) samples are used to do the open test. A good performance of 92.18 % accuracy is achieved by proposed system.

This report describes AlGaAs/GaAs HBT ICs for 20-Gb/s optical transmission, the preamplifier and optical modulator driver circuits, and those ICs for 10-Gb/s clock extraction circuits, the rectifier and phase shifter circuits. These ICs were fabricated using our developed hetero guard-ring fully self-aligned HBT (HG-FST) fabrication process. The Pt-Ti-Pt-Au multimetal system was also used as a base ohmic metal to reduce base contact resistance, and a high fmax of 105 GHz was obtained. Good results in the HBT IC microwave performances were achieved from the on-wafer measurements. The preamplifiers exhibited the broad bandwidth of 20. 9 GHz. The optical modulator driver performed a sufficiently large output-voltage swing of 4-VP-P at a 20-Gb/s data rate. The rectifier and the phase shifter circuits achieved good operations at 10-Gb/s. These results suggest that these HBT ICs can be applied to 20-Gb/s optical transmission and 10-Gb/s clock extraction systems.

The subject about document image understanding is to extract and classify individual data meaningfully from paper-based documents. Until today, many methods/approaches have been proposed with regard to recognition of various kinds of documents, various technical problems for extensions of OCR, and requirements for practical usages. Of course, though the technical research issues in the early stage are looked upon as complementary attacks for the traditional OCR which is dependent on character recognition techniques, the application ranges or related issues are widely investigated or should be established progressively. This paper addresses current topics about document image understanding from a technical point of view as a survey.

In this paper, the authors present general views of computer vision and image processing based on optimization. Relaxation and regularization in both broad and narrow senses are used in various fields and problems of computer vision and image processing, and they are currently being combined with general-purpose optimization algorithms. The principle and case examples of relaxation and regularization are discussed; the application of optimization to shape description that is a particularly important problem in the field is described; and the use of a genetic algorithm (GA) as a method of optimization is introduced.

The goal of this paper is to present a critical survey of existing literature on an omnidirectional sensing. The area of vision application such as autonomous robot navigation, telepresence and virtual reality is expanding by use of a camera with a wide angle of view. In particular, a real-time omnidirectional camera with a single center of projection is suitable for analyzing and monitoring, because we can easily generate any desired image projected on any designated image plane, such as a pure perspective image or a panoramic image, from the omnidirectional input image. In this paper, I review designs and principles of existing omnidirectional cameras, which can acquire an omnidirectional (360 degrees) field of view, and their applications in fields of autonomous robot navigation, telepresence, remote surveillance and virtual reality.

We have developed a fabrication technique for high-performance high-thermal-stability InP/InGaAs heterojunction bipolar transistors (HBTs) for use in 40-Gb/s ICs. The HBT's T-shaped emitter electrode structure simplifies the fabrication process and enables high controllability of spacing between the emitter and the base electrodes. A highly-C-doped base, grown by gas-source MBE, and a new Pt-based metal system results in a low base resistance. An InP subcollector suppresses thermal runaway of HBTs at high collector current better than a conventional InGaAs subcollector does. Using these techniques, we fabricated a very-high-performance HBT with an extremely high cutoff frequency fT of 235 GHz. The RF measurements show that the collector current at the peak cutoff frequency is inversely proportional to collector thickness. We also fabricated a static 1/2 frequency divider, that can be used for 40-Gb/s optical transmission systems, operating up to 44 GHz. This divider confirmed that the developed HBT is applicable to 40-Gb/s optical transmission ICs.

This paper describes a flip-flop circuit using a directly controlled emitter-follower with a diode-feedback level stabilizer (DC-DF) and a resistor-feedback level stabilizer (DC-RF) for low-power multi-GHz prescalers. The new flip-flop circuit reduces the emitter-follower current and gains both high-frequency operation and low-power. A dual modulus (4/5) prescaler using this circuit technology was fabricated with a 0.35 µm BiCMOS process. The current draw of the prescaler using the DC-RF is 34% smaller than conventional LCML circuits. The DC-RF prescaler operates at 2.11 GHz with a total current consumption of 1.03 mA. In addition, the circuit operates with a supply voltage of down to 2.4 V by using the resistor level-shift clock-driver.

This paper describes a newly developed FET Coupled Logic (FCL) circuit that operates at very high frequencies with very low supply voltages below 3.3 V. An FCL circuit consists of NMOS source-coupled transistor pairs for current switches, load resistors, emitter followers and current sources that are controlled by a band-gap reference bias generator. The characteristics and performance are discussed by comparing this circuit with other high-speed circuits. The optimal circuit parameters for FCL circuits are also discussed, and the fact is noted that a larger swing voltage enhances the circuit's performance. The simulated delay of a 0.25 µm FCL circuit is less than 15 ps for a 2.5 V power supply, and the simulated maximum toggle frequencies are over 5 GHz and 10 GHz at 2.5 V and 3.3 V power supply, respectively. The simulation results show that FCL circuits achieve the best performance among the current mode circuits, which include ECL circuits, NMOS source-coupled logic circuits. The delay of the FCL circuit is less than half that of an ECL circuit. The maximum toggle frequency of the FCL circuit is about triple that of NMOS source-coupled logic circuit. Because the FCL circuit uses low-cost CMOS-based BiCMOS technologies, its cost performance is superior to ECL circuits that require expensive base-emitter self-aligned processes and trench isolation processes. Using depletion-mode NMOS transistors for current switches can lower the minimum supply voltage for FCL circuits and it is below 1.5 V. The FCL circuit is a promising logic gate circuit for multi-Gbit/s tele/data communication LSIs.

This paper proposes a novel sequential coherent preambleless demodulator that uses phase signals instead of complex signals in the automatic frequency control (AFC) and carrier recovery circuits. The proposed demodulator employs a phase-combined frequency error detection circuit and dual loop AFC circuit to achieve fast frequency acquisition and low frequency jitter. It also adopts an open loop carrier recovery scheme with a sample hold circuit after the carrier filter to ensure carrier signal stability within a packet. It is shown that the frame error rate performance of the proposed demodulator is superior, by 30%, to that offered by differential detection in a frequency selective Rayleigh fading channel. The hardware size of the proposed demodulator is about only 1/10 that of a conventional coherent demodulator employing complex signals.

Feedback of class memberships is incorporated into multimodal pattern classifiers and their unsupervised learning algorithm is presented. Classification decision at low levels is revised by the feedback information which also enables the reconstruction of patterns at low levels. The effects of the feedback are examined for the McGurk effect by using a simple model.

This paper describes a 2.5-Gb/s optical receiver and transmitter chipset consisting of a preamplifier, a main amplifier, a clock and data recovery (CDR) circuit, and a laser-diode (LD) driver. Low-voltage and adjustment-free circuit techniques are introduced in order to achieve low cost and low power circuits. Circuit adjustments are eliminated by using a multi-stage automatic offset canceling technique in the main amplifier, and by using a PLL structure with a sample-and-hold technique in the CDR circuit. For power reduction, ICs are operated at a power supply voltage of -3 V. Fabricating the ICs by a 0.5-µm Si bipolar process makes it possible to achieve 2.5-Gb/s receiver and transmitter operation with a total power dissipation of 1.04 W. Especially significant is that the receiver ICs need no external devices and adjustments.

This paper is consisting of the two novel EMC technologies that we have been developed in our laboratory. The first is the technology for measuring the RF (Radio Frequency) nearby magnetic field and estimation of the RF current in the printed circuit board (PCB) by using the small loop antenna with multi-layer PCB structure developed by our laboratory. I introduce the application of our small loop antenna with its physical structure and the analysis of the nearby magnetic field distribution of the printed circuit board applying the discrete Wavelet analysis. We can understand the behavior of the digital circuit in detail, and we can also take measures to meet the specification about the electromagnetic radiation from the digital circuit from the higher order of priority by using these technologies. The second is our proposing novel technology for reducing the electromagnetic radiation from the digital equipment by taking notice of the improvement of the de-coupling in the PCB. We confirmed the remarkable effect of this technology by redesigning the motherboard of the small-sized computer.