We experimentally demonstrate the ultrafast and high-repetition capabilities of a polarization-discriminating symmetric Mach-Zehnder (PD-SMZ) all-optical switch. This switch, as well as an original symmetric Mach-Zehnder (SMZ) all-optical switch, is based on a highly efficient but slowly relaxing band-filling effect that is resonantly excited in a passive InGaAsP bulk waveguide. By using a mechanism that cancels out the effect of the slow relaxation, ultrafast switching is attained. We achieve a switching time of 200 fs and demultiplexing of 1.5 Tbps, showing the applicability of the SMZ or PD-SMZ all-optical switches to optical demultiplexing of well over 1 Tbps for the first time. High-repetition capability, which is another important issue apart from the switching speed, is also verified by using control pulses at a repetition rate of 10.5 GHz. We also discuss the use of nonlinearity in a semiconductor optical amplifier to further reduce the control-pulse energy.

We have been working on a project called ParaBIT (for parallel inter-board optical interconnection technology) to achieve large-capacity switching systems. The ParaBIT module being developed as the first step in this project is a front-end module with 40 channels providing throughput of 28 Gb/s, cost-effectiveness and compactness. To realize the module, this project has developed five novel technologies: (1) 850-nm 10-ch Vertical-cavity Surface-emitting laser (VCSEL) arrays as very cost-effective light sources, (2) new high-density multiport bare fiber connectors that do not need a ferrule and spring, (3) passive optical alignment using polymeric optical waveguide film with a 45-degree mirror for coupling to the optical array chips and the waveguide, (4) transferred multichip bonding to mount optical array chips on a substrate with a positioning error of only a few micrometers, and (5) simple electronic circuits with a fixed-decision-level receiver and an APC-less transmitter, and low power consumption. Experimental results show that the design targets of throughput of 700 Mb/s per channel and a compact and cost-effectiveness structure were met. Thus, ParaBIT is a promising technology for large-capacity switching systems.

Divisor-Skip Wavelength Division Multiplexing (DS-WDM) ring is an optical interconnection network for workstation clusters or parallel machines which can connect various number of nodes easily using wavelength division multiplexing techniques. However, the wavelength-ordered routing algorithm proposed for the DS-WDM ring requires complicated processes in each router. Here, a new routing algorithm called the comparing dimensional number routing algorithm for the DS-WDM ring is proposed and evaluated. Although the diameter and average distance are almost same as traditional wavelength-ordered routing, the cost and latency are much reduced.

Since the inception of optical networking, a goal has been to create an all-optical network. The rapid breakthrough for WDM in point to point links has brought this prospect considerably closer, however, at the same time, questions regarding the scalability of the all-optical network remain. In this paper, we review our recent research in this area, partly performed within the European Union project METON (METropolitan Optical Network), and discuss the all-optical approach and different optoelectronic alternatives, mainly of the 2R (reamplify and reshape) type.

Wavelength division multiplex (WDM) photonic networks are expected as the key for the global communication infrastructure. Recent increase of communication demands require large-scale highly-dense WDM systems, which results in severe requirements for optical cross-connect systems, such as cross-talk specification. In this paper, we propose a new optical path cross-connect system (OPXC) using matrix-WDM scheme, which makes it possible to reduce cross-talk requirements of WDM filters and to construct OPXC in modular structures. The matrix-WDM scheme is a concept of two-layered optical paths, which provides wavelength group managements in the fiber dispersion equalization and EDFA gain equalization.

We discuss optimal estimation of the current location of a mobile robot by matching an image of the scene taken by the robot with the model of the environment. We first present a theoretical accuracy bound and then give a method that attains that bound, which can be viewed as describing the probability distribution of the current location. Using real images, we demonstrate that our method is superior to the naive least-squares method. We also confirm the theoretical predictions of our theory by applying the bootstrap procedure.

Digital Signal Processors with complex arithmetic capability (DSP-C) are useful for various applications. In this paper, we propose a method for the effective implementation of specific circuits with real coefficients on DSP-C. DSP-C has special hardware such as a complex multiplier so that a complex calculation can be performed with only one instruction. First, we show that nodes with two real coefficient input branches can be implemented by complex multiplications. We apply this implementation to 2D circuits and transversal circuits with real coefficients. Next, we introduce a new computational mode (Advanced mode) and a new multiplier into PSI, a kind of DSP-C which has been proposed already, in order to process the circuits effectively. The effectiveness of the proposed method is shown by simulation in the last part.

A direct conversion transmitter IC including a proposed frequency doubler, a quadrature modulator, and a 3-bit variable attenuator was fabricated using BiCMOS technology with fT of 12 GHz. This architecture employing frequency doubler is intended for realizing wireless terminals that are low in cost and small in size. The architecture is effective for reducing serious interference between PA and VCO by making the VCO frequency different from that of PA. The proposed frequency doubler comprises a current-driven 90 phase-shifter and an ECL-EXOR circuit for both low power operation and wide input power range of local oscillator (LO). The proposed frequency doubler keeps high output power even when rectangular wave from LO is applied owing to use of the current-driven 90 phase-shifter instead of a voltage-driven 90 phase-shifter. An LO leakage of less than -25 dBc, an image rejection ratio in excess of 45 dBc, and a maximum attenuation of 21 dB were measured. The transmitter IC successfully operates at LO power above -15 dBm and consumes 68 mA from 2.7 V power supply voltage. An active die size is 1.5 mm3 mm.

Thanks to rapid progress in computer technology and VLSI technology, we are approaching the stage where ordinary PCs will be able to handle real-time video signals as easily as they handle text data. First, features and applications of the video compression standard MPEG2 are surveyed as a typical video processing. It is clarified that real-time capability becomes more important as applications of MPEG2 widely spread. The trends of video coding in LSIs are summarized. And it is shown that the most advanced encoder/decoder LSI has an improved price-performance ratio that allows it to be adopted in consumer equipment. Finally, future directions of parallel architecture in video processing are surveyed in terms of special-purpose and general-purpose processing. The special approach has always taken the lead in video processing using sophisticated hardware-oriented parallel architectures. The general-purpose architecture method has gradually evolved in accordance with a software-oriented architecture. Both approaches will continue to evolve into a new stage by selecting possible parallel architectures such as multimedia instruction sets and process-level parallelism, and applying them in compound use. The so-called super processor architecture will emerge in the near future and it will be an ideal method that can manage rapid increase in requirements of capability and applicability in video processing.

The system architectures, which allow a high performance fully balanced (FB) system based on ordinary/modified single-ended opamps to be implemented, are investigated and the basic and general requirements are formulated. Two new methods of an FB analog system design, which contribute towards achieving both a high performance IC system implementation and a great reduction of the design time are presented. It is shown that a single-ended system based on any type of opamp (rail-to-rail, constant gm, etc. ), realized in any technology (CMOS, bipolar, BiCMOS, GaAs), can be easily and effectively converted to its FB counterpart in a very practical way. Using the proposed rules, any FB system implementation with opamps (data converter, modulator, filter, etc. ) requires only a single-ended system version design and the drawbacks related to a conventional FB system design are avoided. The principles of the design are pointed out and they are verified by experimental results.

Multi-input floating gate differential amplifier (FGDA) is proposed which can perform any convolution operation with differential structure and feedback loop. All operations are in the voltage mode. Only one terminal is required for the negative feedback which can suppress distortions due to mismatches of active elements. Possible applications include intelligent image sensor, where fully parallel DCT operation can be performed. A prototype chip is fabricated which is functional. A preliminary test result is reported.

DC offset causes performance degradation in signal processing systems especially for high-speed applications. A new offset cancellation method that relaxes the requirement for the offset of the circuit components in the differential analog data path to about 10 times larger is introduced. This method moves the adjusting target from analog-to-digital converter (ADC) to its input buffer and adjusts DC level of ADC input to its center before the final offset cancellation. It eliminates post-production adjustment such as fuse trimming, which increases the cost and TAT in manufacturing and testing. Execution and simulation times are shortened down to 1/9 for less settling time in buffer and with improved logic. An automatic quick offset calibration circuit is implemented in a small silicon space in a high-speed hard disk drive (HDD) channel with 0.25-µm four-layer metal CMOS process. The measured data show this method works effectively in this system.

Since the inception of optical networking, a goal has been to create an all-optical network. The rapid breakthrough for WDM in point to point links has brought this prospect considerably closer, however, at the same time, questions regarding the scalability of the all-optical network remain. In this paper, we review our recent research in this area, partly performed within the European Union project METON (METropolitan Optical Network), and discuss the all-optical approach and different optoelectronic alternatives, mainly of the 2R (reamplify and reshape) type.

State of the arts on guided-wave optical switch arrays are reviewed. In this paper, electro-optic Ti:LiNbO3 devices are mainly described in comparison with crosspoint switch element structures and switch array architectures. Packaging technologies and stability problems are discussed for practical system applications. Recent development on other materials such as semiconductor waveguides, thermo-optic glass/polymer waveguides are also reviewed briefly.

Recent work in the area of ultrafast optical time-division multiplexed (OTDM) networking at MIT Lincoln Laboratory is presented. A scalable helical local area network or HLAN architecture, presented elsewhere as an architecture well-suited to ultrafast OTDM LANs and MANs, is considered in the context of wide area networking. Two issues arise in scaling HLAN to the wide area. The first is protocol extension, and the second is supporting the required bandwidth on the long-haul links. In this paper we discuss these challenges and describe progress made in both architecture and technologies required for scaling HLAN to the wide area.

In this paper, a scheme to remove clouds and their shadows from remotely sensed images of Landsat TM over land has been proposed. The scheme uses the image fusion technique to automatically recognize and remove contamination of clouds and their shadows, and integrate complementary information into the composite image from multitemporal images. The cloud regions can be detected on the basis of the reflectance differences with the other regions. Based on the fact that shadows smooth the brightness changes of the ground, the shadow regions can be detected successfully by means of wavelet transform. Further, an area-based detection rule is developed in this paper and the multispectral characteristics of Landsat TM images are used to alleviate the computational load. Because the wavelet transform is adopted for the image fusion, artifacts are invisible in the fused images. Finally, the performance of the proposed scheme is demonstrated experimentally.

Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on all-optical wavelength converter types based on semiconductor optical amplifiers.

A method for circular pattern recognition in a binary image and its implementation onto an FPGA are described. The proposed method is based on the template matching method using a modified matching degree. This method is implementable onto an FPGA and can realize a real-time system. The usefulness of the proposed method was confirmed by numerical simulations. The real-time performance was confirmed by experiments on the FPGA designed by using Verilog-HDL CAD tool.

Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on all-optical wavelength converter types based on semiconductor optical amplifiers.

For the purpose of realizing a new intelligent system and its simplified VLSI implementation, we propose a new nonvolatile analog memory called "switched diffusion analog memory with feedback circuit (FBSDAM). " FBSDAM has linear writing and erasing characteristics. Therefore, FBSDAM is useful for memorizing an analog value exactly. We also propose a new analog content-addressable memory (CAM) which has neural-like learning and discriminating functions which discriminate whether an incoming pattern is an unknown pattern or a stored pattern. We design and fabricate the CAM using FBSDAM by means of the 4µm double-poly single-metal CMOS process and nonvolatile analog memory technology which are developed by us. The chip size is 3.1 mm3.1 mm. We estimate that the CAM is composed of 50 times fewer transistors and requires 70 times fewer calculation steps than a typical digital computer implemented using similar technology.