Multi-input floating gate differential amplifier (FGDA) is proposed which can perform any convolution operation with differential structure and feedback loop. All operations are in the voltage mode. Only one terminal is required for the negative feedback which can suppress distortions due to mismatches of active elements. Possible applications include intelligent image sensor, where fully parallel DCT operation can be performed. A prototype chip is fabricated which is functional. A preliminary test result is reported.

The system architectures, which allow a high performance fully balanced (FB) system based on ordinary/modified single-ended opamps to be implemented, are investigated and the basic and general requirements are formulated. Two new methods of an FB analog system design, which contribute towards achieving both a high performance IC system implementation and a great reduction of the design time are presented. It is shown that a single-ended system based on any type of opamp (rail-to-rail, constant gm, etc. ), realized in any technology (CMOS, bipolar, BiCMOS, GaAs), can be easily and effectively converted to its FB counterpart in a very practical way. Using the proposed rules, any FB system implementation with opamps (data converter, modulator, filter, etc. ) requires only a single-ended system version design and the drawbacks related to a conventional FB system design are avoided. The principles of the design are pointed out and they are verified by experimental results.

Digital Signal Processors with complex arithmetic capability (DSP-C) are useful for various applications. In this paper, we propose a method for the effective implementation of specific circuits with real coefficients on DSP-C. DSP-C has special hardware such as a complex multiplier so that a complex calculation can be performed with only one instruction. First, we show that nodes with two real coefficient input branches can be implemented by complex multiplications. We apply this implementation to 2D circuits and transversal circuits with real coefficients. Next, we introduce a new computational mode (Advanced mode) and a new multiplier into PSI, a kind of DSP-C which has been proposed already, in order to process the circuits effectively. The effectiveness of the proposed method is shown by simulation in the last part.

Thanks to rapid progress in computer technology and VLSI technology, we are approaching the stage where ordinary PCs will be able to handle real-time video signals as easily as they handle text data. First, features and applications of the video compression standard MPEG2 are surveyed as a typical video processing. It is clarified that real-time capability becomes more important as applications of MPEG2 widely spread. The trends of video coding in LSIs are summarized. And it is shown that the most advanced encoder/decoder LSI has an improved price-performance ratio that allows it to be adopted in consumer equipment. Finally, future directions of parallel architecture in video processing are surveyed in terms of special-purpose and general-purpose processing. The special approach has always taken the lead in video processing using sophisticated hardware-oriented parallel architectures. The general-purpose architecture method has gradually evolved in accordance with a software-oriented architecture. Both approaches will continue to evolve into a new stage by selecting possible parallel architectures such as multimedia instruction sets and process-level parallelism, and applying them in compound use. The so-called super processor architecture will emerge in the near future and it will be an ideal method that can manage rapid increase in requirements of capability and applicability in video processing.

DC offset causes performance degradation in signal processing systems especially for high-speed applications. A new offset cancellation method that relaxes the requirement for the offset of the circuit components in the differential analog data path to about 10 times larger is introduced. This method moves the adjusting target from analog-to-digital converter (ADC) to its input buffer and adjusts DC level of ADC input to its center before the final offset cancellation. It eliminates post-production adjustment such as fuse trimming, which increases the cost and TAT in manufacturing and testing. Execution and simulation times are shortened down to 1/9 for less settling time in buffer and with improved logic. An automatic quick offset calibration circuit is implemented in a small silicon space in a high-speed hard disk drive (HDD) channel with 0.25-µm four-layer metal CMOS process. The measured data show this method works effectively in this system.

State of the arts on guided-wave optical switch arrays are reviewed. In this paper, electro-optic Ti:LiNbO3 devices are mainly described in comparison with crosspoint switch element structures and switch array architectures. Packaging technologies and stability problems are discussed for practical system applications. Recent development on other materials such as semiconductor waveguides, thermo-optic glass/polymer waveguides are also reviewed briefly.

Recent work in the area of ultrafast optical time-division multiplexed (OTDM) networking at MIT Lincoln Laboratory is presented. A scalable helical local area network or HLAN architecture, presented elsewhere as an architecture well-suited to ultrafast OTDM LANs and MANs, is considered in the context of wide area networking. Two issues arise in scaling HLAN to the wide area. The first is protocol extension, and the second is supporting the required bandwidth on the long-haul links. In this paper we discuss these challenges and describe progress made in both architecture and technologies required for scaling HLAN to the wide area.

A method for circular pattern recognition in a binary image and its implementation onto an FPGA are described. The proposed method is based on the template matching method using a modified matching degree. This method is implementable onto an FPGA and can realize a real-time system. The usefulness of the proposed method was confirmed by numerical simulations. The real-time performance was confirmed by experiments on the FPGA designed by using Verilog-HDL CAD tool.

In this paper, a scheme to remove clouds and their shadows from remotely sensed images of Landsat TM over land has been proposed. The scheme uses the image fusion technique to automatically recognize and remove contamination of clouds and their shadows, and integrate complementary information into the composite image from multitemporal images. The cloud regions can be detected on the basis of the reflectance differences with the other regions. Based on the fact that shadows smooth the brightness changes of the ground, the shadow regions can be detected successfully by means of wavelet transform. Further, an area-based detection rule is developed in this paper and the multispectral characteristics of Landsat TM images are used to alleviate the computational load. Because the wavelet transform is adopted for the image fusion, artifacts are invisible in the fused images. Finally, the performance of the proposed scheme is demonstrated experimentally.

Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on all-optical wavelength converter types based on semiconductor optical amplifiers.

Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on all-optical wavelength converter types based on semiconductor optical amplifiers.

A 116 arrayed waveguide grating multiplexer operating around 1550 nm has been realized using newly synthesized fluorinated poly(arylene ethers). The channel spacing is 0.8 nm (100 GHz). The insertion loss of the multiplexer is 17-20 dB and the cross talk is less than -15 dB. The propagation loss of a rib waveguide is less than 0.5 dB/cm at 1550 nm.

To enhance the extinction ratio (ER) of NRZ-to-inverted-RZ converter based on cross-gain compression of a semiconductor optical amplifier (SOA), a modified terahertz optical asymmetric demultiplexer (TOAD) is cascaded. ER is improved from 1.6-6.7 dB to 5.4-14.5 dB, depending on the intensity of input optical NRZ signal. The proposed NRZ-to-inverted-RZ converter enhances and regulates ER to a high value (14.5 dB) for very wide optical NRZ signal intensity range.

A large scale optical switch array based on guided-wave technology using banyan network architecture is demonstrated. Banyan network architecture is the simplest NN network connecting a input port to all the output ports. A banyan network optical switch array serves as a base for constructing many classes of switch networks, as we propose in this report. We fabricated a 3232 switch and measured its characteristics. Drive voltage was about 12 V and extinction ratio was 18 dB, and the average insertion loss was 18 dB. Preliminary experiments were conducted on a 6464 device. The use of proton exchanged waveguides makes a 10 mm radius of curvature feasible.

State of the arts on guided-wave optical switch arrays are reviewed. In this paper, electro-optic Ti:LiNbO3 devices are mainly described in comparison with crosspoint switch element structures and switch array architectures. Packaging technologies and stability problems are discussed for practical system applications. Recent development on other materials such as semiconductor waveguides, thermo-optic glass/polymer waveguides are also reviewed briefly.

An optical cell buffer (OCB) for use in photonic ATM switch, is needed in order to resolve contention between optical cells. A 320-Gb/s-throughput switch system with 32 wavelength channels requires a buffer size of 13 and a wavelength bandwidth of 25 nm. We developed an optical cell buffer with a four-nested-taps configuration and fabricated it with electroabsorption gates and gain clamped optical amplifiers. The output level variation, which determines the stability of operating condition, is less than 2.4 dB under typical conditions and the insertion loss variation is suppressed to within 5 dB. This OCB can be used in a 320-Gb/s photonic ATM switch.

This paper proposes a 3-stage ATM switch architecture that uses optical WDM (wavelength division multiplexing) grouped links and dynamic bandwidth sharing. The proposed architecture has two features. The first is the use of WDM technology which makes the number of cables used in the system proportional to system size. The second is the use of dynamic bandwidth sharing among WDM grouped links. This prevents the statistical multiplexing gain offered by WDM from falling even if switching system becomes large. A performance evaluation confirms the scaleability and cost-effectiveness of the proposed architecture. It is scaleable in terms of the number of cables and admissible load. We show how the appropriate wavelength signal speed can be determined to implement the switch in a cost-effective manner. Therefore, the proposed architecture will suit future high-speed multimedia ATM networks.

In learning of feed-forward neural networks, so-called 'training error' is often minimized. This is, however, not related to the generalization capability which is one of the major goals in the learning. It can be interpreted as a substitute for another learning which considers the generalization capability. Admissibility is a concept to discuss whether a learning can be a substitute for another learning. In this paper, we discuss the case where the learning which minimizes a training error is used as a substitute for the projection learning, which considers the generalization capability, in the presence of noise. Moreover, we give a method for choosing a training set which satisfies the admissibility.

This paper presents an algorithm for viewpoint-based similarity discernment of linguistic concepts on Semantic Network Array Processor (SNAP). The viewpoint-based similarity discernment plays a key role in retrieving similar propositions. This is useful for advanced knowledge processing areas such as analogical reasoning and case-based reasoning. The algorithm assumes that a knowledge base is constructed for SNAP, based on information acquired from the WordNet linguistic database. The algorithm identifies paths on the knowledge base between each given concept and a given viewpoint concept, then computes a similarity degree between the two concepts based on the number of nodes shared by the paths. A small scale knowledge base was constructed and an experiment was conducted on a SNAP simulator that demonstrated the feasibility of this algorithm. Because of SNAP's scalability, the algorithm is expected to work similarly on a large scale knowledge base.

Based on a previous work on handwritten Japanese kanji character recognition, a postprocessing system for handwritten Japanese address recognition is proposed. Basically, the recognition system is composed of CombNET-II, a general-purpose large-scale character recognizer and MMVA, a modified majority voting system. Beginning with a set of character candidates, produced by a character recognizer for each character that composes the input word and a lexicon, an interpretation to the input word is generated. MMVA is used in the postprocessing stage to select the interpretation that accumulates the highest score. In the case of more than one possible interpretation, the Conflict Analyzing System calls the character recognizer again to generate scores for each character that composes each interpretation to determine the final output word. The proposed word recognition system was tested with 2 sets of handwritten Japanese city names, and recognition rates higher than 99% were achieved, demonstrating the effectiveness of the method.