Spot-size-converter integrated semiconductor optical amplifiers have been developed as gate elements for optical switch matrices. An S-shape waveguide has been introduced to prevent re-coupling of unguided light to the output fiber. An angled-facet structure effectively suppressed light reflection at the end facets. Consequently, a high extinction ratio of 70 dB and a high fiber-to-fiber gain of 20 dB were achieved. Sufficient optical coupling characteristics to a flat-ended single-mode fiber with a coupling loss of 3.5 dB were also demonstrated.

This paper proposes a method to transform a CORDIC ARMA lattice filter, which is originally realized for signal analysis, into a signal synthesis lattice filter (CORDIC ARMA lattice synthesis filter). In order to perform such a transformation and then obtain the CORDIC ARMA lattice synthesis filter, we must implement the followings with CORDIC: (1) the structure of the altered lattice filter; and (2) an angle calculation module. However, we cannot achieve such an implementation as an extension of the CORDIC ARMA lattice filter algorithm. Therefore, this paper proposes CORDIC implementation schemes for both the structure and module, and then we realize the CORDIC ARMA lattice synthesis filter. By using CORDIC processors, the elementary sections of the CORDIC ARMA lattice synthesis filter are efficiently implemented without any multipliers. Since the obtained signal synthesis lattice filter consists of dedicated CORDIC processors, it keeps the advantage of the CORDIC ARMA lattice filter, that is a simple structure.

Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on all-optical wavelength converter types based on semiconductor optical amplifiers.

We propose novel all-optical functional devices using waveguide X-junctions with localized third order optical nonlinearity, where one branch is made from a Kerr-like nonlinear material and the rest are made from linear ones. All-optical switching operations can be obtained because of bistable like nonlinear dispersion characteristics in linear and nonlinear coupled guided-wave systems. The performances of the devices are analyzed by the Beam Propagation Method (BPM) modified for nonlinear waveguides combined with the nonlinear normal mode analysis. The methods to construct the waveguides with localized nonlinearity are also discussed by utilizing the technologies for the selective control of a band-gap energy of semiconductor Multi Quantum Well (MQW) structures and the performances of the designed devices are presented.

We have been working on a project called ParaBIT (for parallel inter-board optical interconnection technology) to achieve large-capacity switching systems. The ParaBIT module being developed as the first step in this project is a front-end module with 40 channels providing throughput of 28 Gb/s, cost-effectiveness and compactness. To realize the module, this project has developed five novel technologies: (1) 850-nm 10-ch Vertical-cavity Surface-emitting laser (VCSEL) arrays as very cost-effective light sources, (2) new high-density multiport bare fiber connectors that do not need a ferrule and spring, (3) passive optical alignment using polymeric optical waveguide film with a 45-degree mirror for coupling to the optical array chips and the waveguide, (4) transferred multichip bonding to mount optical array chips on a substrate with a positioning error of only a few micrometers, and (5) simple electronic circuits with a fixed-decision-level receiver and an APC-less transmitter, and low power consumption. Experimental results show that the design targets of throughput of 700 Mb/s per channel and a compact and cost-effectiveness structure were met. Thus, ParaBIT is a promising technology for large-capacity switching systems.

We propose a real-time low-rate video compression algorithm using fixed-rate multi-stage hierarchical vector quantization. Vector quantization is suitable for mobile computing, since it demands small computation on decoding. The proposed algorithm enables transmission of 10 QCIF frames per second over a low-rate 29.2 kbps mobile channel. A frame is hierarchically divided by sub-blocks. A frame of images is compressed in a fixed rate at any video activity. For active frames, large sub-blocks for low resolution are mainly transmitted. For inactive frames, smaller sub-blocks for high resolution can be transmitted successively after a motion-compensated frame. We develop a compression system which consists of a host computer and a memory-based processor for the nearest neighbor search on VQ. Our algorithm guarantees real-time decoding on a poor CPU.

A 116 arrayed waveguide grating multiplexer operating around 1550 nm has been realized using newly synthesized fluorinated poly(arylene ethers). The channel spacing is 0.8 nm (100 GHz). The insertion loss of the multiplexer is 17-20 dB and the cross talk is less than -15 dB. The propagation loss of a rib waveguide is less than 0.5 dB/cm at 1550 nm.

The hybrid electrical/optical multi-chip integration technique for optical modules for optical network system has been developed. Employing the technique, a 44 broadcast-and-select type optical matrix switch module has been realized. The module consists of four sets of silica waveguide 1 : 4 splitters/4 : 1 combiners, four 4-channel arrays of polarization insensitive semiconductor optical amplifiers with spot-size converters as optical gates, printed wiring chips for electrical wiring and single mode fibers for optical signal interface on planar waveguide platform fabricated by atmospheric pressure chemical vapor deposition. All the gates and the wiring chips were mounted precisely onto the platform at once in flip-chip manner by self-align technique using AuSn solder bumps. Coupling loss between the waveguide and the SOA gate was estimated to be 4.5 dB. Averaged fiber-to-fiber signal gain, on-off ratio and polarization dependent loss for each of the signal paths was 7 dB 2 dB, more than 40 dB and 0.5 dB, respectively. High speed 10 Gb/s photonic cell switching as short as 2 nsec has been successfully achieved.

State of the arts on guided-wave optical switch arrays are reviewed. In this paper, electro-optic Ti:LiNbO3 devices are mainly described in comparison with crosspoint switch element structures and switch array architectures. Packaging technologies and stability problems are discussed for practical system applications. Recent development on other materials such as semiconductor waveguides, thermo-optic glass/polymer waveguides are also reviewed briefly.

An optical cell buffer (OCB) for use in photonic ATM switch, is needed in order to resolve contention between optical cells. A 320-Gb/s-throughput switch system with 32 wavelength channels requires a buffer size of 13 and a wavelength bandwidth of 25 nm. We developed an optical cell buffer with a four-nested-taps configuration and fabricated it with electroabsorption gates and gain clamped optical amplifiers. The output level variation, which determines the stability of operating condition, is less than 2.4 dB under typical conditions and the insertion loss variation is suppressed to within 5 dB. This OCB can be used in a 320-Gb/s photonic ATM switch.

A large scale optical switch array based on guided-wave technology using banyan network architecture is demonstrated. Banyan network architecture is the simplest NN network connecting a input port to all the output ports. A banyan network optical switch array serves as a base for constructing many classes of switch networks, as we propose in this report. We fabricated a 3232 switch and measured its characteristics. Drive voltage was about 12 V and extinction ratio was 18 dB, and the average insertion loss was 18 dB. Preliminary experiments were conducted on a 6464 device. The use of proton exchanged waveguides makes a 10 mm radius of curvature feasible.

We experimentally demonstrate the ultrafast and high-repetition capabilities of a polarization-discriminating symmetric Mach-Zehnder (PD-SMZ) all-optical switch. This switch, as well as an original symmetric Mach-Zehnder (SMZ) all-optical switch, is based on a highly efficient but slowly relaxing band-filling effect that is resonantly excited in a passive InGaAsP bulk waveguide. By using a mechanism that cancels out the effect of the slow relaxation, ultrafast switching is attained. We achieve a switching time of 200 fs and demultiplexing of 1.5 Tbps, showing the applicability of the SMZ or PD-SMZ all-optical switches to optical demultiplexing of well over 1 Tbps for the first time. High-repetition capability, which is another important issue apart from the switching speed, is also verified by using control pulses at a repetition rate of 10.5 GHz. We also discuss the use of nonlinearity in a semiconductor optical amplifier to further reduce the control-pulse energy.

To enhance the extinction ratio (ER) of NRZ-to-inverted-RZ converter based on cross-gain compression of a semiconductor optical amplifier (SOA), a modified terahertz optical asymmetric demultiplexer (TOAD) is cascaded. ER is improved from 1.6-6.7 dB to 5.4-14.5 dB, depending on the intensity of input optical NRZ signal. The proposed NRZ-to-inverted-RZ converter enhances and regulates ER to a high value (14.5 dB) for very wide optical NRZ signal intensity range.

Spot-size-converter integrated semiconductor optical amplifiers have been developed as gate elements for optical switch matrices. An S-shape waveguide has been introduced to prevent re-coupling of unguided light to the output fiber. An angled-facet structure effectively suppressed light reflection at the end facets. Consequently, a high extinction ratio of 70 dB and a high fiber-to-fiber gain of 20 dB were achieved. Sufficient optical coupling characteristics to a flat-ended single-mode fiber with a coupling loss of 3.5 dB were also demonstrated.

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |Vt|+2 Vds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2µm N-well process with a 3 V supply are given.

Crosstalk from digital to analog circuits can be causative of operation fails in analog-digital mixed LSIs. This paper describes modeling techniques and simulation strategies of the substrate coupling noise. A macroscopic substrate noise model that expresses the noise as a function of logic state transition frequencies among digital blocks is proposed. A simulation system based on the model is implemented in the mixed signal simulation environment, where performance degradation of the 2nd order ΔΣADC coupled to digital noise sources is clearly simulated. These results indicate that the proposed behavioral modeling approach allows practicable full chip substrate noise simulation measures.

A chaotic noise is one of the most important implements for information processing such as neural networks. It has been suggested that chaotic neural networks have high performance ability for information processing. In this paper, we report two designs of a compact chaotic noise generator for large integration circuits using CMOS technology. The chaotic noise is generated using map chaos. We design both of the logistic map type and the tent map type circuits. These chaotic noise generators are compact as compared with the other circuits. The results show that the successful chaotic operations of the circuits because of the positive Lyapunov number. We calculate the Lyapunov exponents to certify the results of the chaotic operations. However, it is hard to estimate its accurate number for noisy data using the conventional method. And hence, we propose the modified calculation of the Lyapunov exponent for noisy data. These two circuits are expected to be utilized for various applications.

The security of the ElGamal-type signature scheme is based on the difficulty of solving a discrete logarithm problem. If a random value that is introduced in the signing procedure is small, then the time for generating signature can be reduced. This strategy is particularly advantageous when a signer uses a smart card. In this paper, we show that the secret key can be computed efficiently if the random value is less than O(q) where q is the order of the generator.

This paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Data path allocation is achieved by a controllability and observability balance allocation technique which is based on testability analysis at register-transfer level. Scheduling, on other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. Contrary to other works in which the scheduling and allocation tasks are performed independently, our approach integrates scheduling and allocation by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. Additionally, since sequential loops are widely recognized to make a design hard-to-test, a complete (functional and topological) loop analysis is performed at register-transfer level in order to avoid loop creation during the integrated test synthesis process. With a variety of synthesis benchmarks, experimental results show clearly the advantages of the proposed algorithm.

This paper gives an overview of research activities on high performance databases in Japan. It focuses on parallel algorithms for relational databases and data mining, parallel approaches for object-oriented databases, and parallel disk systems. Studies surveyed in this paper are carried out mainly by database researchers in Japanese universities under the Grant-in-Aid for Scientific Research (1996-1998).