An unbiased estimation method for symmetric noncausal ARMA model parameters is presented. The proposed algorithm works in two steps: first, a spectrally equivalent causal system is identified by lattice whitening filter and then the equivalent noncausal system is reconstructed. For AR system with noise or ARMA system without noise, the proposed method does not need any iteration method nor any optimization procedure. An estimation method of noise variance when the observation is made in noisy situation is discussed. The potential capabilities of the algorithm are demonstrated by using some numerical examples.

This paper presents a heuristic algorithm that minimizes the delay of the given circuit through a two-pass cell selection in cell-based design. First, we introduce a new graph, called candidate web, which conveniently represents all cell combinations available for the implementation of the given circuit. We, then, present an efficient method to obtain a tentative set of optimal cells, while estimating the delay of the longest path between each cell and the primary output on the candidate web. In this step, multiple cells are allowed to bind the same logic gate. Finally, we describe how the proposed approach actually selects the optimal cells from the tentative set, which would minimize the circuit delay. Experimental results on a set of benchmarks show that the proposed approach is effective and efficient in minimizing the delay of the given circuit.

The conventional synthesis procedure of discrete time sparsely interconnected neural networks (DTSINNs) for associative memories may generate the cells with only self-feedback due to the sparsely interconnected structure. Although this problem is solved by increasing the number of interconnections, hardware implementation becomes very difficult. In this letter, we propose the DTSINN system which stores the 2-dimensional discrete Walsh transforms (DWTs) of memory patterns. As each element of DWT involves the information of whole sample data, our system can associate the desired memory patterns, which the conventional DTSINN fails to do.

This paper describes a flip-flop circuit using a directly controlled emitter-follower with a diode-feedback level stabilizer (DC-DF) and a resistor-feedback level stabilizer (DC-RF) for low-power multi-GHz prescalers. The new flip-flop circuit reduces the emitter-follower current and gains both high-frequency operation and low-power. A dual modulus (4/5) prescaler using this circuit technology was fabricated with a 0.35 µm BiCMOS process. The current draw of the prescaler using the DC-RF is 34% smaller than conventional LCML circuits. The DC-RF prescaler operates at 2.11 GHz with a total current consumption of 1.03 mA. In addition, the circuit operates with a supply voltage of down to 2.4 V by using the resistor level-shift clock-driver.

Phase performance in a fiber optic temperature sensor using a mode-division multiplex is studied. The phase shift due to the temperature change of a multimode graded-index optical fiber is analyzed. The intensity fluctuation by the interference of two modes is estimated in computer simulation.

Computational sensor (smart sensor, vision chip in other words) is a very small integrated system, in which processing and sensing are unified on a single VLSI chip. It is designed for a specific targeted application. Research activities of computational sensor are described in this paper. There have been quite a few proposals and implementations in computational sensors. Firstly, their approaches are summarized from several points of view, such as advantage vs. disadvantage, neural vs. functional, architecture, analog vs. digital, local vs. global processing, imaging vs. processing, new processing paradigms. Then, several examples are introduced which are spatial processings, temporal processings, A/D conversions, programmable computational sensors. Finally, the paper is concluded.

The Scalable-Delay-Insensitive (SDI) model is proposed for high-performance asynchronous system design. In this paper, we focus on checking whether a circuit under SDI model satisfies some untimed properties, and formally show that checking these properties in the SDI model can be reduced to checking the same properties in the bounded delay model. This result suggests that the existing verification algorithms for the bounded delay model can be used for the verification of SDI circuits, which significantly helps the designers of SDI circuits.

This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 hours, making this method 5 times more efficient than conventional methods

This paper presents a neural circuit using PWM technique based on an analog-digital merged circuit architecture. Some new PWM circuit techniques are proposed. A bipolar-weighted summation circuit is described which attains 8-bit precision in SPICE simulation at 5 V supply voltage by compensating parasitic capacitance effects. A high performance differential-type latch comparator which can discriminate 1 mV difference at 100 MHz in SPICE simulation is also described. Next, we present a prototype chip fabricated using a 0.6µm CMOS process. The measurement results demonstrate that the overall precision in the weighted summation and the sigmoidal transformation is 5 bits. A neural network has been constructed using the prototype chips, and the experimental results for realizing the XOR function have successfully verified the basic neural operation.

The hybrid electrical/optical multi-chip integration technique for optical modules for optical network system has been developed. Employing the technique, a 44 broadcast-and-select type optical matrix switch module has been realized. The module consists of four sets of silica waveguide 1 : 4 splitters/4 : 1 combiners, four 4-channel arrays of polarization insensitive semiconductor optical amplifiers with spot-size converters as optical gates, printed wiring chips for electrical wiring and single mode fibers for optical signal interface on planar waveguide platform fabricated by atmospheric pressure chemical vapor deposition. All the gates and the wiring chips were mounted precisely onto the platform at once in flip-chip manner by self-align technique using AuSn solder bumps. Coupling loss between the waveguide and the SOA gate was estimated to be 4.5 dB. Averaged fiber-to-fiber signal gain, on-off ratio and polarization dependent loss for each of the signal paths was 7 dB 2 dB, more than 40 dB and 0.5 dB, respectively. High speed 10 Gb/s photonic cell switching as short as 2 nsec has been successfully achieved.

Recent work in the area of ultrafast optical time-division multiplexed (OTDM) networking at MIT Lincoln Laboratory is presented. A scalable helical local area network or HLAN architecture, presented elsewhere as an architecture well-suited to ultrafast OTDM LANs and MANs, is considered in the context of wide area networking. Two issues arise in scaling HLAN to the wide area. The first is protocol extension, and the second is supporting the required bandwidth on the long-haul links. In this paper we discuss these challenges and describe progress made in both architecture and technologies required for scaling HLAN to the wide area.

We propose and demonstrate for the first time in our knowledge, an optical switch circuit architecture furnishing with the "Bridge and Switch" function, conforming to ITUT-T Recommendation G. 841 Annex A for optical Add-Drop Multiplexers (ADMs) in WDM four-fiber ring networks. This function enables optical ADMs to revert automatically from the switching state to their idle state just after the recovery of failure, that is indispensable for the extra traffic accommodation to enhance efficiency of the network operation. oWe have developed the optical ADM nodes employing the proposed optical switch circuit for each wavelength, arrayed-waveguide gratings (AWGs) and Er-doped fiber amplifiers. In the demonstration, transmission characteristics of the cascaded optical ADM nodes without regenerative repeaters have been verified at first. We have confirmed the ring protection and the automatic protection switching (APS) sequence which includes the automatic reversion in the optical ADM nodes with proposed optical switch circuits.

Since the inception of optical networking, a goal has been to create an all-optical network. The rapid breakthrough for WDM in point to point links has brought this prospect considerably closer, however, at the same time, questions regarding the scalability of the all-optical network remain. In this paper, we review our recent research in this area, partly performed within the European Union project METON (METropolitan Optical Network), and discuss the all-optical approach and different optoelectronic alternatives, mainly of the 2R (reamplify and reshape) type.

A novel testing-pad placement method has been developed to greatly improve E-beam observability for multi-level wiring LSIs. In the method, testing pads connecting a lower-metal-layer wire with a top-metal-layer electrode are positioned in the design layout, making removal of the insulator unnecessary. The method features i) pad placement in unoccupied areas in mask patterns to avoid increases in chip size, ii) minimized pad size through the use of stacked vias so that the pads can be placed on as many wire nodes as possible, iii) placement as far as possible from the nearby wires to avoid local field effects, and iv) allocation of one testing pad to one circuit node to minimize the number of testing pads. These measures give us a practical pad-placement method, that has little influence on LSI design. It was shown that the proposed method yielded a dramatic improvement of observability from 13-33% to 88-99% in actual layouts of 0.25-µm ASICs with 20k, 120k, and 390k gates. It was also found that local field effects from nearby wires are negligible for almost all the testing pads. This approach will enable the use of E-beam testing on LSIs made with 0.25-µm technology and the even more sophisticated process technologies to come.

Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on all-optical wavelength converter types based on semiconductor optical amplifiers.

We have been working on a project called ParaBIT (for parallel inter-board optical interconnection technology) to achieve large-capacity switching systems. The ParaBIT module being developed as the first step in this project is a front-end module with 40 channels providing throughput of 28 Gb/s, cost-effectiveness and compactness. To realize the module, this project has developed five novel technologies: (1) 850-nm 10-ch Vertical-cavity Surface-emitting laser (VCSEL) arrays as very cost-effective light sources, (2) new high-density multiport bare fiber connectors that do not need a ferrule and spring, (3) passive optical alignment using polymeric optical waveguide film with a 45-degree mirror for coupling to the optical array chips and the waveguide, (4) transferred multichip bonding to mount optical array chips on a substrate with a positioning error of only a few micrometers, and (5) simple electronic circuits with a fixed-decision-level receiver and an APC-less transmitter, and low power consumption. Experimental results show that the design targets of throughput of 700 Mb/s per channel and a compact and cost-effectiveness structure were met. Thus, ParaBIT is a promising technology for large-capacity switching systems.

Wavelength division multiplex (WDM) photonic networks are expected as the key for the global communication infrastructure. Recent increase of communication demands require large-scale highly-dense WDM systems, which results in severe requirements for optical cross-connect systems, such as cross-talk specification. In this paper, we propose a new optical path cross-connect system (OPXC) using matrix-WDM scheme, which makes it possible to reduce cross-talk requirements of WDM filters and to construct OPXC in modular structures. The matrix-WDM scheme is a concept of two-layered optical paths, which provides wavelength group managements in the fiber dispersion equalization and EDFA gain equalization.

We experimentally demonstrate the ultrafast and high-repetition capabilities of a polarization-discriminating symmetric Mach-Zehnder (PD-SMZ) all-optical switch. This switch, as well as an original symmetric Mach-Zehnder (SMZ) all-optical switch, is based on a highly efficient but slowly relaxing band-filling effect that is resonantly excited in a passive InGaAsP bulk waveguide. By using a mechanism that cancels out the effect of the slow relaxation, ultrafast switching is attained. We achieve a switching time of 200 fs and demultiplexing of 1.5 Tbps, showing the applicability of the SMZ or PD-SMZ all-optical switches to optical demultiplexing of well over 1 Tbps for the first time. High-repetition capability, which is another important issue apart from the switching speed, is also verified by using control pulses at a repetition rate of 10.5 GHz. We also discuss the use of nonlinearity in a semiconductor optical amplifier to further reduce the control-pulse energy.

We have been working on a project called ParaBIT (for parallel inter-board optical interconnection technology) to achieve large-capacity switching systems. The ParaBIT module being developed as the first step in this project is a front-end module with 40 channels providing throughput of 28 Gb/s, cost-effectiveness and compactness. To realize the module, this project has developed five novel technologies: (1) 850-nm 10-ch Vertical-cavity Surface-emitting laser (VCSEL) arrays as very cost-effective light sources, (2) new high-density multiport bare fiber connectors that do not need a ferrule and spring, (3) passive optical alignment using polymeric optical waveguide film with a 45-degree mirror for coupling to the optical array chips and the waveguide, (4) transferred multichip bonding to mount optical array chips on a substrate with a positioning error of only a few micrometers, and (5) simple electronic circuits with a fixed-decision-level receiver and an APC-less transmitter, and low power consumption. Experimental results show that the design targets of throughput of 700 Mb/s per channel and a compact and cost-effectiveness structure were met. Thus, ParaBIT is a promising technology for large-capacity switching systems.