This paper describes a new high resolution algorithm for the two-dimensional (2-D) frequency estimation problem, which, in particular, is noise insensitive in view of the fact that in many practical applications the contaminated noise may not be white noise. For this purpose, the approach is set in the context of higher-order statistics (HOS), which has demonstrated to be an effective approach under a colored noise environment. The algorithm begins with the consideration of the fourth-order moments of the available 2-D data. Two auxiliary matrices, constituted by a novel stacking of the diagonal slice of the computed fourth-order moments, are then introduced and through which the two frequency components can be precisely determined, respectively, via matrix factorizations along with the subspace rotational invariance (SRI) technique. Simulation results are also provided to verify the proposed algorithm.

Parallel Transaction Processing (TP) systems have great potential to serve the ever-increasing demands for high transaction processing rate. This potential, however, may not be reached due to the data contention and the widely-used two-phase locking (2PL) Concurrency Control (CC) method. In this paper, a distributed locking-based CC policy called LWDC (Local Wait-Depth Control) was proposed for dealing with this problem for the shared-nothing parallel TP system. On the basis of the LWDC policy, an algorithm called LWDCk was designed. Using simulation LWDCk was compared with the 2PL and the base-line Distributed Wait-Depth Limited (DWDL) CC methods. Simulation studies show that the new algorithm offers better system performance than those compared.

A GaAs power amplifier IC has been developed for 1. 9-GHz digital mobile communication applications, such as the handsets of the Japanese personal handy phone system (PHS), which was assembled into a very small 0. 012-cc surface mount plastic package. This power amplifier using refractory WNx/W self-aligned gate MESFETs with p-pocket layers can operate with high efficiency and low distortion with a single 3-V supply. A very low dissipated current of 119 mA was obtained with an output power of 21. 1 dBm and a low 600-kHz adjacent channel leakage power (ACP) of -63 dBc for π/4-shifted quadrature phase shift keying (QPSK) modulated input.

In [1], approximate eigenvalues and eigenvectors are defined and algorithms to compute them are described. However, the algorithms require a certain condition: the eigenvalues of M modulo S are all distinct, where M is a given matrix with polynomial entries and S is a maximal ideal generated by the indeterminate in M. In this paper, we deal with the construction of approximate eigenvalues and eigenvectors when the condition is not satisfied. In this case, powers of approximate eigenvalues and eigenvectors become, in general, fractions. In other words, approximate eigenvalues and eigenvectors are expressed in the form of Puiseux series. We focus on a matrix with univariate polynomial entries and give complete algorithms to compute the approximate eigenvalues and eigenvectors of the matrix.

This paper deals with a set of differential operators for calculating the differentials of an observed signal by the Daubechies wavelet and its application for the estimation of the transfer function of a linear system by using non-stationary step-like signals. The differential operators are constructed by iterative projections of the differential of the scaling function for a multiresolution analysis into a dilation subspace. By the proposed differential operators we can extract the arbitrary order differentials of a signal. We propose a set of identifiable filters constructed by the sum of multiple filters with the first order lag characteristics. Using the above differentials and the identifiable filters we propose an identification method for the transfer function of a linear system. In order to ensure the appropriateness and effectiveness of the proposed method some numerical simulations are presented.

This paper proposes an automatic structural programming system. Genetic Programming achieves success for automatic programming using the evolutionary process. However, the approach doesn't deal with the essential program concept in the sense of what is called a program in software science. It is useful that a program be structured by various sub-structures, i. e. subroutines, however, the above-mentioned approach treats a single program as one sequence. As a result of the above problem, there is a lack of reusability, flexibility, and a decreases in the possibility of use as a utilitarian programming system. In order to realize a structural programming system, this paper proposes a method which can generate a program constructed by subroutines, named formula, using the evolutionary process.

This paper proves a general sampling theorem, which is an extension of Shannon's classical theorem. Let o be a closed subspace of square integrable functions and call o a signal space. The main aim of this paper is giving a necessary and sufficient condition for unique existence of the sampling basis {Sn}o without band-limited assumption. Using the general sampling theorem we rigorously discuss a frequency domain treatment and a general signal space spanned by translations of a single function. Many known sampling theorems in signal spaces, which have applications for multiresolution analysis in wavelets theory are corollaries of the general sampling theorem.

The second-generation CMOS current conveyors are developed for high-frequency analog signal processing. It consists of a source follower for the voltage input and a regulated current mirror for the current input and output. The voltage and current input stages are also coupled by a current mirror to reduce the impedance of the current input port. Simulations show that this architecture provides the high input/output conductance ratio and the inherent voltage and current transfer bandwidths extending beyond 100 MHz. The prototype chips fabricated using 0. 6 µm CMOS process have confirmed the simulated performances, though the voltage and current bandwidth are limited to 20 MHz and 35 MHz, respectively, by the built-in capacitances of the bonding pads.

This paper proposes a fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis of digital signal processing hardwares. The objective of the algorithm is to minimize the costs for functional units and registers and to maximize connectivity under given computation time and initiation interval. Incorporating the connectivity in a scheduling stage can reduce multiplexer counts in resource binding. The algorithm maximizes connectivity with maintaining low time complexity and obtains datapath designs with totally small hardware costs in the high-level synthesis environment. The algorithm also resolves inter-iteration data dependencies and thus realizes pipelined datapaths. The experimental results demonstrate that the proposed algorithm reduces the multiplexer counts after resource binding with maintaining low costs for functional units and registers compared with eight conventional schedulers.

For people with serious disability, it is most significant to be able to use the same communication methods, for instance a telephone and an electronic mail system (e-mail), as ordinary people do in order to get a normal life and communicate with other people for leading a social life. In particular, having communications access to an e-mail is a very effective method of communication that enables them to convey their intention to other people directly while at the same time keep their privacy. However, it takes them much time and effort to input an e-mail text on the computer. They also need much support by their attendants. From this point of view, we propose a multi-modal communication system that is composed of a voice recognizer, a pointing device, and a text composer. This system intend to improve the man-machine interface for people with physical disability. In this system, our voice recognition technology plays a key role in providing a good interface between disabled people and the personal computer. When generating e-mail contents, users access the database containing user keywords, and the guidance menu from which they select the appropriate word by voice. Our experimental results suggest that this communication system improves not only the time efficiency of text composition but also the readiness of disabled people to communicate with other people. In addition, our disabled subject on this paper is not able to move his body, legs and hands due to suffer from muscular dystrophy. And he is able to move only his fingers and speak command words with the assistance of a respirator.

This paper describes a neuro-based optimization algorithm for three dimensional (3-D) rectangular puzzles which are the problems to arrange the irregular-shaped blocks so that they perfectly fit into a fixed three dimensional rectangular shape. First, the fitting function of the 3-D block, which means the fitting degree of each irregular block to the neighboring block and the rectangular configuration, is described. Next, the energy function for the 3-D rectangular puzzles is proposed, where the horizontal rotation of the block is also considered. Finally, our optimization method is applied to several examples using the 3-D analog neural array and it is shown that our algorithm is useful for solving 3-D rectangular puzzles.

This paper describes two dimensional (2D) equalization scheme of orthogonal coding multi-carrier CDMA for reverse link of mobile communication systems. The purpose of the 2D equalization is the reduction of Multiple Access Interference (MAI) which is caused by the random access and the different propagation path from each mobile station. The orthogonal coding multi-carrier CDMA multiplexes all mobile stations' data by Code Division Multiplexing (CDM). The 2D coding scheme spreads a preamble signal at time (in subchannel signals) and frequency (between subchannel signals) domains. The 2D decoding scheme estimates transmission delay time and instantaneous fading frequency from preamble signal for individual mobile stations and compensate the received data using these estimation values to reduce MAI.

In this paper, an FPGA (Field Programmable Gate Array)-implementable digital chaos circuit with nonlinear mapping function learning ablility is proposed. The features of this circuit are user-programmability of the mapping functions by on-chip supervised learning, robustness of chaos signal generation based on digital processing, and high-speed and low-cost thanks to its FPGA implementation. The circuit design and analysis are presented in detail. The learning dynamics of the circuit and the quantitization effect to the quasi-chaos generation are analyzed by numerical simulations. The proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This confirmed that the one-dimensional chaos circuit block (except for SRAM's) is implementable on a single FPGA chip and can generate quasi-chaos signals in real time.

We present experimental results for a structural learning method of feed-forward neural-network classifiers using Principal Component Analysis (PCA) network and Species Genetic Algorithm (SGA). PCA network is used as a means for reducing the number of input units. SGA, a modified GA, is employed for selecting the proper number of hidden units and optimizing the connection links. Experimental results show that the proposed method is a useful tool for choosing an appropriate architecture for high dimensions.

In this paper, a new architecture of Multilayer Neural Network (MNN) with on-chip learning for effective hardware implementation is proposed. To reduce the circuit size, threshold function is used as neuron's activating function and simplified back-propagation algorithm is employed to provide on-chip learning capability. The derivative of the activating function is modified to improve the rate of successful learning. The learning performance of the proposed architecture is tested by system-level simulations. Simulation results show that the modified derivative function improves the rate of successful learning and that the proposed MNN has a good generalization capability. Furthermore, the proposed architecture is implemented on field programmable gate array (FPGA). Logic-level simulation and preliminary experiment are conducted to test the on-chip learning mechanism.

In this letter, a digital circuit realizing a Rossler model is proposed. The proposed circuit features exact reproducibility of chaos signals which is desired in chaos-based communication systems. By employing an FPGA implementation, the proposed circuit can achieve high-speed and low-cost realization. The chaotic behavior of the quasi-chaos of the proposed circuit is analyzed by numerical simulations. To confirm the validity of the FPGA implementation, the proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This circuit design showed that the proposed circuit can be implemented onto a single FPGA and can realize real-time chaos generation.

We propose a Generalized Order Statistic Cell Averaging (GOSCA) CFAR detector. The weighted sums of the order statistics in the leading and lagging reference windows are utilized for the background level estimate. The estimate is obtained by averaging the weighted sums. By changing the weighting values, various CFAR detectors are obtained. The main advantage of the proposed GOSCA CFAR detector over the GOS CFAR detector is to reduce a computational time which is critical factor for the real time operation. We also derive unified formulas of the GOSCA CFAR detector under the noncoherent integration scheme. For Swerling target cases, performances of various CFAR detectors implemented using the GOSCA CFAR detector are derived and compared in homogeneous environment, and in the case of multiple targets and clutter edges situations.

This paper describes a theoretical foundation of fuzzy morphological operations and architectural extension of the shared-weight neural network (SWNN). The network performs shift-invariant filtering using fuzzy-morphological operations for feature extraction. The nodes in the feature extraction stage employ the generalized-mean operator to implement fuzzy-morphological operations. The parameters of the SWNN, weights, morphological structuring element and fuzziness, are optimized by the error back-propagation (EBP) training method. The parameter values of the trained SWNN are then implanted into the extended SWNN (ESWNN) which is a simple convolution neural network. The ESWNN architecture dramatically reduces the amount of computation by avoiding segmentation process. The neural network is applied to automatic recognition of a vehicle in visible images. The network is tested with several sequences of images that include targets ranging from no occlusion to almost full occlusion. The results demonstrate an ability to detect occluded targets, while trained with non-occluded ones. In comparison, the proposed network was superior to the Minimum-Average Correlation filter systems and produced better results than the ordinary SWNN.

A novel phase compensation technique for feedback integrators is proposed. By the technique, a zero is obtained without employing extra capacitors. A design of an integrator for IC using the proposed technique is presented. The frequency of the parasitic pole is proportional to the unity gain frequency. It is shown that excess-phase cancellation is obtained at any unity gain frequency.

This paper presents a new architecture for multiple-input signature analyzers. The proposed signature analyzer with Hδ inputs is designed by parallelizing a GLFSR(δ,m), where δ is the number of input signals and m is the number of stages in the feedback shift register. The GLFSR, developed by Pradhan and Gupta, is a general framework for representing LFSR-based signature analyzers. The parallelization technique described in this paper can be applied to any kind of GLFSR signature analyzer, e. g. , SISRs, MISRs, multiple MISRs and MLFSRs. It is shown that a proposed signature analyzer with Hδ inputs requires less complex hardware than either single GLFSR(Hδ,m)s or a parallel construction of the H original GLFSR(δ,m)s. It is also shown that the proposed signature analyzer, while requiring simpler hardware, has comparable aliasing probability with analyzers using conventional GLFSRs for some CUT error models of the same test response length and test time. The proposed technique would be practical for testing CUTs with a large number of output sequences, since the test circuit occupies a smaller area on the LSI chip than the conventional multiple-input signature analyzers of comparable aliasing probability.