A series of transparent photochemical acid-generators (PAGs) has been successfully prepared and investigated to apply ArF excimer-laser lithography. These PAGs were synthesized as new alkylsulfonium salts that have cycloalkyl groups but no aromatic ones. They were almost transparent at 193. 4 nm and have high acid-generation efficiency enough to use for ArF excimer-laser resists. The photochemical reaction of these alkylsulfonium salts occurs mainly due to the S-C bond fission. A resist utilizing the PAGs was capable to resolve a 0. 2µm L/S pattern at a 50-mJ/cm2 dose with an aqueous alkaline developer. These PAGs are promising materials for use in ArF excimer-laser lithography.

We have improved the optical beam induced resistance change (OBIRCH) system so as to detect (1) a current path as small as 10-50 µA from the rear side of a chip, (2) current paths in silicide lines as narrow as 0. 2 µm, (3) high-resistance Ti-depleted polysilicon regions in 0. 2 µm wide silicide lines, and (4) high-resistance amorphous thin layers as thin as a few nanometers at the bottoms of vias. All detections were possible even in observation areas as wide as 5 mm 5 mm. The physical causes of these detections were characterized by focused ion beam and transmission electron microscopy.

We have studied the basic optical and physical characteristics of polymeric optical waveguide films with S-shaped waveguides and 45 mirrors applied as multimode optical interconnection components. The core and cladding of the waveguide films were made of deuterated-polymethylmethacrylate (d-PMMA) and UV-cured resin, respectively. We evaluated the insertion losses of the waveguides, the crosstalk and the 45-mirror losses in these waveguide films and demonstrated that they have low propagation loss. The shrinkage and thermal expansion of the polymeric optical waveguide films are also discussed because of the interest in improving module packaging.

We fabricated a tunable and polarization-insensitive arrayed-waveguide grating (AWG) 1616 multiplexer that operates around the wavelength of 1. 55 µm using fluorinated polyimides. The wavelength channel spacing was 0. 8 nm, and the 3-dB passband width was 0. 26 nm. The insertion loss at each channel was from 8 to 12 dB, and the crosstalk was less than -28 dB. The transmission pass wavelength was tuned over a wide range of 6 nm by heating from 24 to 64. The slope of the temperature dependence of the pass wavelength was -0. 15 nm/, which is ten times that of a silica-based multiplexer. Polarization-insensitivity was achieved by fabricating a film AWG multiplexer, which was formed by removing the silicon substrate and annealing at 350. The polarization-dependent wavelength shift was smaller than the spectrum analyzers wavelength resolution of 0. 1 nm.

This paper presents a test generation method for sequential circuits under IDDQ testing environment and the identification of untestable faults based on the information of illegal states. We consider a short between two signal lines, a short within one gate and a short between two nodes in different gates. The proposed test generation method consists of two techniques. First technique is to use weighted random vectors, and second technique is to use test generator for stuck-at faults. By using the two techniques together, high fault coverage and short computational time can be achieved. Finally experimental results for ISCAS89 benchmark circuits are presented.

We present a high-level synthesis scheme that considers weak testability of generated register-transfer level (RTL) data paths, as well as their area and performance. The weak testability, proposed in our previous work, is a testability measure of RTL data paths for non-scan design. In our scheme, we first extract a condition on resource sharing sufficient for weak testability from a data flow graph before synthesis, and treat the condition as design objectives in the following synthesis tasks. We propose heuristic synthesis algorithms which optimize area and the design objectives under the performance constraint.

Thin films of PTFE (mean molecular weight of source material 8500) were deposited by ionization-assisted deposition (IAD) method at different ion acceleration voltages Va on substrates kept at room temperature. The molecular chains in the film were found to be oriented in parallel with the substrate, and the film has preferential crystal orientation to (100) plane. Although the ion acceleration did not give significant influence on the film orientation and chemical structure, IAD was effective to improve the surface smoothness. The Cu decoration test revealed that the pinhole density in the film is reduced and the insulating capability is improved by depositing the film at Va = 500 V. The result of dielectric loss measurement for Al/PTFE/Al capacitors was in consistency. However, excessive ion acceleration deteriorated the insulating property, probably due to the dielectric breakdown that occurred in the course of deposition.

We will present a partial scan design method based on n-fold line-up structures in order to achieve high fault efficiency and reduce test pattern generation time for practical LSIs. We will also present a partial scan design method based on the state justification of pure load/hold FFs in order to achieve high fault efficiency and reduce the number of scan FFs for practical LSIs with lots of load/hold FFs. Experimental results for practical LSIs show that our presented methods can achieve high fault efficiency (more than 99%) and reduce the number of scan FFs for the LSI with lots of load/hold FFs.

The advantage of random testing is that test application can be performed at a low cost in the BIST scheme. However, not all circuits are random pattern testable due to the existence of random pattern resistant faults. In this paper, we present a method for improving the random pattern testability of logic circuits by partial circuit duplication approach. The basic idea is to detect random pattern resistant faults by using the difference between the duplicated part of a circuit and the original part. Experimental results on benchmark circuits show that high fault coverage can be achieved with a very small amount of hardware overhead.

Hogg and Huberman have proposed a strategy for stabilizing chaotic multi-agent systems. This paper applies their strategy to a resource allocation problem in a manufacturing system consisting of two machines and two types of parts. These part-types conflict each other over resource allocation. We introduce a discrete-time model of the system by using game theory, and examine stability and bifurcation phenomena of its fixed point. We show by computer simulation that chaotic behaviors are observed after successive occurrence of period-doubling bifurcations. It is also shown that the optimal state of the system is stabilized by a reward mechanism.

For two-tier cellular network design, resource management between tiers is an important issue to be studied. In this paper, in order to use the network resources preciously, we considered sharing of the available spectrum between the tiers. We evaluate this sharing for two network architectures. In the first architecture, called System I, DS-CDMA is deployed in both tiers. In the second architecture, called System II, TDMA is deployed for users in the microcell tier and CDMA for macrocell users. Using analytically evaluated intercell interference for a two-tier cellular system, we will show the performance and the allowable system capacity for the above systems.

We have developed a new type of phase interpolation DDS with a digitally controlled delay generator. The new DDS is similar to a sine output DDS in that it produces low spurious signals, but it does not require a sine look-up table. Periodic jitter in the MSB of the DDS accumulator is reduced with the digitally controlled delay generator. Experimental results confirm successful frequency synthesizer operation in which the spurious signal level is successfully reduced to less than that the MSB of the accumulator.

This letter proposes a method to transform normalized ARMA lattice filters, which are originally realized for signal analysis, into signal synthesis lattice filters. Although the transformation method has been proposed for normalized ARMA lattice filters with the MA order which is greater than or equal to the AR order, it has not been done when the AR order is greater than the MA order. With the proposed method, once an ARMA lattice filter with the AR order greater than the MA order is realized, then it can be transformed to the signal synthesis filter.

With the advance of computer technologies, mobile computers can hold many local resources in themselves. In many cases it is impossible to announce local resources on them because almost information announcement systems are not designed for them. In this paper, an information announcement system for mobile computers based on WWW is proposed. The system efficiently announces resources on mobile computers independently of whether they are connected to a network or not, and wherever they are connected. The system can also select suitable announcement methods according to the type of resources. We implement a prototype of proposed system and evaluate it. The result of evaluation confirms effectiveness of the proposed system.

Testing for delay faults is very important in the verification of the timing behavior of digital circuits. When a circuit which is unable to operate at the desired clock speed is identified, it is necessary to locate the delay fault(s) affecting the circuit in order to remedy the situation. In this paper, we present a path-tracing method of multiple gate delay fault diagnosis in combinational circuits. We first present the basic rules for deducing suspected faults based on the multiple gate delay fault assumption. Next, in order to improve diagnostic resolution, we introduce rules for deducing non-existent faults based on the fault-free responses at the primary outputs. Using these rules, we present the detailed method for diagnosing multiple delay faults based on paths sensitized by test-pairs generated for marginal delays and gate delay faults [7]. Finally, we present results obtained from experiments on the ISCAS '85 benchmark circuits. The experimental results show the effectiveness of our method.

Experimental results of 1. 92 Mbps data transmission over a 20 MHz wideband DS-CDMA (W-CDMA) mobile radio link under frequency selective multipath fading are presented. 1. 92 Mbps data were transmitted using an orthogonal multicode transmission scheme. The combined use of antenna diversity reception, RAKE combining, and concatenated channel coding is applied to improve transmission performance. Laboratory and field experimental results demonstrated the possibility of 2 Mbps data transmission in a real fading environment.

Comparative performance evaluation between parallel combinatory CDMA (PC-CDMA) and Direct Sequence CDMA (DS-CDMA) has been conducted for high speed radio communication up to 2 Mbps under a multipath Rayleigh fading environment. For both DS-CDMA and PC-CDMA, user information rate per code of 128 kbps, convolutional code with 1/2 coding rate, the same bit interleaving and QPSK data modulation are applied to get transmission symbol rate of 128 ksps. The chip rate of 4. 096 Mcps is used to investigate the possibility of 2 Mbps transmission using only 5 MHz bandwidth. So the spreading factor of the spreading code is 32 for DS-CDMA. In PC-CDMA, 128 ksps data stream is divided into four 32 ksps data streams and according to the every four bits pattern, corresponding spreading code of spreading factor of 128 and its polarity are selected out of eight candidate spreading codes. In soft decision Viterbi decoding applied to PC-CDMA, branch metric is calculated for every bit by weighting the output levels of the PC-CDMA correlators for eight candidate spreading codes. By computer simulation under vehicular environment model with six multipaths, it has been shown that PC-CDMA can offer more capacity approximately by double than DS-CDMA for both downlink and uplink under the condition such as for vehicular for BER of 10-3, and 2 Mbps transmission per cell for downlink is possible not only in isolated cell condition but also in omni cell condition by PC-CDMA.

A simple digital circuit based on the probabilistic cellular automata is proposed whose temporal evolution generates 1/f noise over many frequency decades. The N cells with internal states form a one-dimensional network and probabilistically interact with nearest-neighbor ones. The internal state of the cell is either the stable state or the unstable state. Each cell obeys simple rules as follows. When the excitatory signal is applied to the cell in the stable state, the state changes to the unstable state. On the other hand, when the state is unstable, the state changes to the stable state, and then the cell generates the excitatory signal. The excitatory signal is applied to the cell which is randomly chosen between the right side cell and the left side cell. The edge condition of the network is open, so that the excitatory signal can leave both the first edge and the last edge. The excitatory signal is randomly added to the first edge of the network at intervals of T time. Then the sequential interactions may occur like avalanche breakdown. After the interactions, the network goes to the equilibrium state. Considering that the breakdown happen simultaneously and assigning the stable state and the unstable state to 0 and 1, respectively, one can get the random pulse stream on the internal state of each cell. The power spectra of pulse streams are Lorentzian with various pole frequencies. The probability distribution of the pole frequency is inversely proportional to the frequency, i. e. , obeys Zipf law. Then the total sum of the internal states of all cells fluctuates following 1/f power law. The frequency range following 1/f power law can be easily varied by changing the number of the cells for the summation. A prototype generator using 15 cells generates 1/f noise over 3 frequency decades. This simple circuit is composed of only full adders and needs not complex components such as multipliers. Fine-tuning of any parameters and precise components also are not needed. Therefore integration into one chip using standard CMOS process is easy.

This paper presents a design of CMOS Chua-type analog chaos circuit by using a signal-flow-graph (SFG) method. In this circuit, the transmittance of a nonlinear element is realized by an OTA with a feedback resistor, and other linear elements are realized by op-amp based circuits. The proposed circuit is insensitive to the finite admittance of OTA's and to the parasitics of resistors except a feedback resistor in the nonlinear element. The performance and chaotic behavior of the proposed circuit are confirmed by SPICE simulations.

Two types of CPW-fed active antenna for television receivers, printed on thin dielectric film, are analyzed numerically and experimentally and their broadband operations are reported. The actual gain of the receiving active antenna is expressed in terms of the transducer power gain of the amplifier circuit and the effective length of the passive antenna. Between the feed point of the passive antenna element and the CPW, the silicon transistor 2SC2585 or 2SC3604 is integrated with a dipole antenna or loop antenna. The actual gains of a dipole antenna with 24 cm length are more than 8 dBd (relative gain to the standard half-wave dipole) at frequencies from 470 to 770 MHz for television channels 13-62 in Japan. In the case of a loop antenna with a size of 25. 8 cm12 cm, actual gains of more than 3. 5 dBd are obtained for channels 1-12, from 90 to 222 MHz, and more than 6. 5 dBd for channels 13-62, from 470 to 770 MHz.