An injection-locked clock recovery circuit (CRC) with quadrature outputs based on multiplexed oscillator is presented. The CRC can operate at a half-rate speed to provide an adequate locking range with reasonable jitter and power consumption because both clock edges sample the data waveforms. Implemented by 0.18-µm CMOS technique, experimental results demonstrate that it can achieve the phase noise of the recovered clock about -121.55 dBc/Hz at 100-kHz offset and -129.58 dBc/Hz at 1-MMz offset with 25 MHz lock range, while operating at the input data rate of 1.55 Gb/s.

Self embedding watermarking is a technique used for tamper detection, localization and recovery. This letter proposes a novel self embedding scheme, in which the halftone version of the host image is exploited as a watermark, instead of a JPEG-compressed version used in most existing methods. Our scheme employs a pixel-wise permuted and embedded mechanism and thus overcomes some common drawbacks of the previous methods. Experimental results demonstrate our technique is effective and practical.

In a Cognitive Radio system, it is essential to recognize and avoid sources of interference signals. This paper describes a study on a location sensing scheme for interference signals, which utilizes multi-beam phased array antenna for cognitive wireless networks. This paper also elucidates its estimation accuracy of the interference location for the radio communication link using an OFDM signal such as WiMAX. Furthermore, we use the frequency spectrum of the received OFDM interference signal, to create a method that can estimate the propagation status. This spectrum can be monitored by using a software defined radio receiver.

In this paper, we propose a novel network selection algorithm considering power consumption in hybrid wireless networks for vertical handover. CDMA, WiBro, WLAN networks are candidate networks for this selection algorithm. This algorithm is composed of the power consumption prediction algorithm and the final network selection algorithm. The power consumption prediction algorithm estimates the expected lifetime of the mobile station based on the current battery level, traffic class and power consumption for each network interface card of the mobile station. If the expected lifetime of the mobile station in a certain network is not long enough compared the handover delay, this particular network will be removed from the candidate network list, thereby preventing unnecessary handovers in the preprocessing procedure. On the other hand, the final network selection algorithm consists of AHP (Analytic Hierarchical Process) and GRA (Grey Relational Analysis). The global factors of the network selection structure are QoS, cost and lifetime. If user preference is lifetime, our selection algorithm selects the network that offers longest service duration due to low power consumption. Also, we conduct some simulations using the OPNET simulation tool. The simulation results show that the proposed algorithm provides longer lifetime in the hybrid wireless network environment.

The concept of placing enormous Solar Power Satellite (SPS) systems in space represents one of a handful of new technological options that might provide large scale, environmentally clean base load power to terrestrial markets. Recent advances in space exploration have shown a great need for antennas with high resolution, high gain and low side lobe level (SLL). The last characteristic is of paramount importance especially for the Microwave Power Transmission (MPT) in order to achieve higher transmitting efficiency (TE) and higher beam collection efficiency (BCE). In order to achieve low side lobe levels, statistical methods play an important role. Various interesting properties of a large antenna arrays with randomly, uniformly and combined spacing of elements have been studied, especially the relationship between the required number of elements and their appropriate spacing from one viewpoint and the desired SLL, the aperture dimension, the beamwidth and TE from the other. We propose a new unified approach in searching for reducing SLL by exploiting the interaction of deterministic and stochastic workspaces of proposed algorithms. Our models indicate the side lobe levels in a large area around the main beam and strongly reduce SLL in the entire visible range. A new concept of designing a large antenna array system is proposed. Our theoretic study and simulation results clarify how to deal with the problems of side lobes in designing a large antenna array, which seems to be an important step toward the realization of future SPS/MPT systems.

Cryptographic hash functions have been widely studied and are used in many current systems. Though much research has been done on the security of hash functions, system designers cannot determine which hash function is most suitable for a particular system. The main reason for this is that the current security classification does not correspond very well to the security requirements of practical systems. This paper describes a new classification which is more suitable for designing real-life systems. This classification is the result of a new qualitative classification and a new quantitative classification. We show a mapping between each class and standard protocols. In addition, we show new requirements for four types of hash function for a future standard.

A concurrent model of computation and a language based on the model for bit-level operation are useful for developing asynchronous and concurrent programs compositionally, which frequently use bit-level operations. Some examples are programs for video games, hardware emulation (including virtual machines), and signal processing. However, few models and languages are optimized and oriented to bit-level concurrent computation. We previously developed a visual programming language called A-BITS for bit-level concurrent programming. The language is based on a dataflow-like model that computes using processes that provide serial bit-level operations and FIFO buffers connected to them. It can express bit-level computation naturally and develop compositionally. We then devised a concurrent computation model called APEC (Asynchronous Program Elements Connection) for bit-level concurrent computation. This model enables precise and formal expression of the process of computation, and a notion of primitive program elements for controlling and operating can be expressed synthetically. Specifically, the model is based on a notion of uniform primitive processes, called primitives, that have three terminals and four ordered rules at most, as well as on bidirectional communication using vehicles called carriers. A new notion is that a carrier moving between two terminals can briefly express some kinds of computation such as synchronization and bidirectional communication. The model's properties make it most applicable to bit-level computation compositionally, since the uniform computation elements are enough to develop components that have practical functionality. Through future application of the model, our research may enable further research on a base model of fine-grain parallel computer architecture, since the model is suitable for expressing massive concurrency by a network of primitives.

Numerical function generators (NFGs) realize arithmetic functions, such as ex,sin(πx), and , in hardware. They are used in applications where high-speed is essential, such as in digital signal or graphics applications. We introduce the edge-valued binary decision diagram (EVBDD) as a means of reducing the delay and memory requirements in NFGs. We also introduce a recursive segmentation algorithm, which divides the domain of the function to be realized into segments, where the given function is realized as a polynomial. This design reduces the size of the multiplier needed and thus reduces delay. It is also shown that an adder can be replaced by a set of 2-input AND gates, further reducing delay. We compare our results to NFGs designed with multi-terminal BDDs (MTBDDs). We show that EVBDDs yield a design that has, on the average, only 39% of the memory and 58% of the delay of NFGs designed using MTBDDs.

For formal verification of large-scale digital circuits, a method using satisfiability checking of logic with equality and uninterpreted functions has been proposed. This logic, however, does not consider specific properties of functions or predicates at all, e.g. associative property of addition. In order to ease this problem, we introduce "equivalence constraint" that is a set of formulas representing the properties of functions and predicates, and check the satisfiability of formulas under the constraint. In this report, we show an algorithm for checking satisfiability with equivalence constraint and also experimental results.

The clonal selection algorithm (CS), inspired by the basic features of adaptive immune response to antigenic stimulus, can exploit and explore the solution space parallelly and effectively. However, antibody initialization and premature convergence are two problems of CS. To overcome these two problems, we propose a chaotic distance-based clonal selection algorithm (CDCS). In this novel algorithm, we introduce a chaotic initialization mechanism and a distance-based somatic hypermutation to improve the performance of CS. The proposed algorithm is also verified for numerous benchmark traveling salesman problems. Experimental results show that the improved algorithm proposed in this paper provides better performance when compared to other metaheuristics.

We propose a new label recognition system for photonic label routing network. Binary-coded labels in binary phase-shift-keying format are considered. The system consists of an optical waveguide circuit with tree-structure passive asymmetric X-junctions and time gates. The system uses self-routing propagation of an identifying bit by performing interference with address bits. The identifying bit is placed in advance of the address bits in the label. The identifying bit pulse is routed to the destination output port corresponding to the code of the address. The operation principle is described. It is shown that all the binary number codes can be recognized with this system. We discuss the feasibility of the system by evaluating its crosstalk. To reduce the crosstalk, an improved scheme is also presented. The label recognition operation with the optical waveguide device is verified by numerical simulation using the finite-difference beam propagation method.

Microwave measurement methods necessary to characterize copper-clad dielectric laminate substrates are reviewed to realize more precise design of planar circuits: that is, the balanced-type circular disk resonator method for the relative complex permittivity in the normal direction εrn and tan δn, the cavity resonator method and the cut-off waveguide method for one in the tangential direction εrt and tan δt, and the dielectric resonator method for the surface and interface conductivity of copper foil σs and σi. The measured results of the frequency and temperature dependences of these parameters are presented for a PTFE substrate and a copper-clad glass cloth PTFE laminate substrate.

One method for achieving high-speed waveform digitizing uses time-interleaved A-D Converters (ADCs). It is known that, in this method, using multiple ADCs enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique. This method can be applied to any number of interleaved ADCs, and it does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead.

We have been investigating a new class of ubiquitous services, called Activity Logging, which takes advantage for private and public sensors and the RFID tags on real-world objects. The purpose of Activity Logging is to digitally record users' interests with real-world objects and users' context to describe the users' activity. Such digital information acquired from a range of sensors and tags, if being accumulated, forms a great data source for users to recall their activities later or to share the activities with others. This paper explores the design space to realize Activity Logging, and proposes a simple mobile device called Activity Recorder that marries public and private sensors to provide a powerful Activity Logging service. An Activity Recorder contains a range of private sensors, and has communication capability to work with public sensors around the user.

In this paper, we investigate the critical low coverage problem of position aware localized efficient broadcast in mobile ad hoc ubiquitous sensor networks and propose a generic framework for it. The framework is to determine a small subset of nodes and minimum transmission radiuses based on snapshots of network state (local views) along the broadcast process. To guarantee the accuracy of forward decisions, based on historical location information nodes will predict neighbors' positions at future actual transmission time and then construct predicted and synchronized local views rather than simply collect received "Hello" messages. Several enhancement technologies are also proposed to compensate the inaccuracy of prediction and forward decisions. To verify the effectiveness of our framework we apply existing efficient broadcast algorithms to it. Simulation results show that new algorithms, which are derived from the generic framework, can greatly increase the broadcast coverage ratio.

Our purpose is to estimate conditional probabilities of output labels in multiclass classification problems. Adaboost provides highly accurate classifiers and has potential to estimate conditional probabilities. However, the conditional probability estimated by Adaboost tends to overfit to training samples. We propose loss functions for boosting that provide shrinkage estimator. The effect of regularization is realized by shrinkage of probabilities toward the uniform distribution. Numerical experiments indicate that boosting algorithms based on proposed loss functions show significantly better results than existing boosting algorithms for estimation of conditional probabilities.

Exploiting layer7 context is an effective approach to improving the accuracy of detecting malicious messages in network intrusion detection/prevention systems (NIDS/NIPSs). Layer7 context enables us to inspect message formats and the message exchanged order. Unfortunately, layer7-aware NIDS/NIPSs pose crucial implementation issues because they require full TCP and IP reassembly without losing 1) complete prevention, 2) performance, 3) application transparency, or 4) transport transparency. Complete prevention means that the NIDS/NIPS should prevent malicious messages from reaching target applications. Application transparency means not requiring any modifications to and/or reconfiguration of server and client applications. Transport transparency is not to disrupt the end-to-end semantics of TCP/IP. To the best of our knowledge, none of the existing approaches meet all of these requirements. We have developed an efficient mechanism for layer7-aware NIDS/NIPSs that does meet the above requirements. Our store-through does this by forwarding each out-of-order or IP-fragmented packet immediately after copying the packet even if it has not been checked yet by an NIDS/NIPS sensor. Although the forwarded packet might turn out to be a part of an attack message, the store-through mechanism can successfully defend against the attack by blocking one of the subsequent packets that contain another part of attack message. Testing of a prototype in Linux kernel 2.4.30 demonstrated that the overhead of our mechanism is negligible compared with that of a simple IP forwarder even with the presence of out-of-order and IP-fragmented packets. In addition, the experimental results suggest that the CPU and memory usage incurred by our store-through is not significant.

The present paper describes an implementation of an intrusion detection system (IDS) on an FPGA for 10 Gigabit Ethernet. The system includes an exact string matching circuit for 1,225 Snort rules on a single device. A number of studies have examined string matching circuits for IDS. However, implementing a circuit that processes a large rule set at high throughput is difficult. In a previous study, we proposed a method for generating an NFA-based string matching circuit that has expandability of processing data width and drastically reduced resource requirements. In the present paper, we implement an IDS circuit that processes 1,225 Snort rules at 10 Gbps with a single Xilinx Virtex-II Pro xc2vp-100 using the NFA-based method. The proposed circuit also provides packet filtering for an intrusion protection system (IPS). In addition, we developed a tool for automatically generating the Verilog HDL source code of the IDS circuit from a Snort rule set. Using the FPGA and the IDS circuit generator, the proposed system is able to update the matching rules corresponding to new intrusions and attacks. We implemented the IDS circuit on an FPGA board and evaluated its accuracy and throughput. As a result, we confirmed in a test that the circuit detects attacks perfectly at the wire speed of 10 Gigabit Ethernet.

Ubiquitous computing and the upcoming broadcast-and-communication convergence require networks that provide very complex services. In particular, networks are needed that can service several users or terminals at various times or places with various application-layer functions that can be changed at a high response speed by adding high-speed processing at the network edge. I present a query-transaction acceleration appliance that uses a dynamic reconfigurable processor (DRP) and enables high-speed stateful packet-by-packet self-reconfiguration to achieve that requirement. This appliance processes at high speeds, has flexible application layer functions that are changeable with a high-speed response, and uses direct packet I/O bypassing memory, hierarchical interconnection of processors, and stateful packet-by-packet self-reconfiguration. In addition, the DRP enables the fabrication of a compact and electric-power-saving appliance. I made a prototype and implemented several transport/application layer functions, such as TCP connection control, auto-caching of server files, uploading cache data for server, and selection/insertion/deletion/update of data for a database. In an experimental evaluation in which four kinds of query-transactions were continually executed in order, I found that the appliance achieved four functions changeable at a high response speed (within 1 ms), and a processing speed (2,273 transactions/sec.) 18 times faster than a PC with a 2-GHz processor.

In this paper, we propose a method of controlling personal data disclosure based on LooM (Loosely Managed Privacy Protection Method) that prevents a malicious third party from identifying a person when he/she gets context-aware services using personal data. The basic function of LooM quantitatively evaluates the anonymity level of a person who discloses his/her data, and controls the personal-data disclosure according to the level. LooM uses a normalized entropy value for quantifying the anonymity. In this version of the LooM, the disclosure control is accomplished by adding two new functions. One is an abstracting-function that generates abstractions (or summaries) from the raw personal data to reduce the danger that the malicious third party might identify the person who discloses his/her personal data to the party. The other function is a unique-value-masking function that hides the unique personal data in the database. These functions enhance the disclosure control mechanism of LooM. We evaluate the functions using simulation data and questionnaire data. Then, we confirm the effectiveness of the functions. Finally, we show a prototype of a crime-information-sharing service to confirm the feasibility of these functions.