In this paper we propose a new application of Wu's mechanical theorem proving method to reconstruct polyhedra in 3-D space from their projection image. First we set up three groups of equations. The first group is of the geometric relations expressing that vertices are on a plane segment, on a line segment, and forming angle in 3-D space. The second is of those relations on image plane. And the rest is of the relations between the vertices in 3-D space and their correspondence on image plane. Next, we classify all the groups of equations into two sets, a set of hypotheses and a conjecture. We apply this method to seven cases of models. Then, we apply Wu's method to prove that the hypotheses follow the conjecture and obtain pseudodivided remainders of the conjectures, which represent relations of angles or lengths between 3-D space and their projected image. By this method we obtained new geometrical relations for seven cases of models. We also show that, in the region in image plane where corresponding spatial measures cannot reconstructed, leading coefficients of hypotheses polynomials approach to zero. If the vertex of an image angle is in such regions, we cannot calculate its spatial angle by direct manipulation of the hypothesis polynomials and the conjecture polynomial. But we show that by stability analysis of the pseudodivided remainder the spatial angles can be calculated even in those regions.

In this paper, we propose an algorithm of O(|V|min{k,|V|,|A|}|A|) time complexity for finding all k-edge-connected components of a given digraph D=(V,A) and a positive integer k. When D is symmetric, incorporating a preprocessing reduces this time complexity to O(|A|+|V|2+|V|min{k,|V|}min{k|V|,|A|}), which is at most O(|A|+k2|V|2).

Surface reconstruction and visualization from sparse and incomplete surface data is a fundamental problem and has received growing attention in both computer vision and graphics. This paper presents a computational scheme for realistic visualization of free-formed surfaces from 3D range images. The novelty of this scheme is that by integrating computer vision and computer graphics techniques, we dynamically construct a mesh representation of the arbitrary view of the surfaces, from a view-invariant shape description obtained from 3D range images. We outline the principle of this scheme and describle the frame work of a graphical reconstruction model, we call arbitrarily oriented meshes', which is developed based on differential geometry. The experimental results on real range data of human faces are shown.

In the PICASSO, a system for the facial caricature generation, as the basic mechanisms to extract the individuality features of faces and to deform the features have been already introduced, it is expected to realize an autonomous mechanism to evaluate facial caricatures. The evaluation should be based on the framework of human visual cognition. In the PICASSO, some visual illusions such as the Wundt-Fick illusion and the Ponzo illusion for example, are applied to evaluate the shapes of the facial parts such as eyebrows, nose, mouth and face contour, in the deformation process. In many cases, as well-deformed caricatures are evaluated to be successful, it is confirmed that the utilization of the visual illusion is effective to evaluate the results of caricatures. In this paper, some experimental results are presented together with the definition of the evaluation measures and the further subjects.

A high-speed data communication service such as inter-LAN is one of many services possible with ATM-based B-ISDN. Design objectives were to simplify the connection setup procedure, to ensure efficient utilization of network capacity, and to reduce delay in servers. These objectives were met in a B-ISDN service trial system featuring distributed connectionless servers connected by permanent virtual channels and cell-by-cell processing in the connectionless server. The system's eight connectionless servers accommodate up to 256 subscriber network interfaces. The authors discuss how multicast can be provided in ATM-based connectionless data networks for inter-LAN communications. Four possible configurations, distinguished by copy function (multicast/broadcast) and on functional arrangement in the inter-connectionless server network (centralized/distributed), are presented. The configurations are compared from perspectives of required hardware and network capacity. The distributed broadcast function is shown the most reasonable solution.

We examine the characteristics of the past successful m-valued I2L and ROMs that have been designed and we discuss the reasons of their success and withdraw. We look at the problems associated with scaling of m-valued CMOS current mode circuits. Then we discuss the tolerance issue, the respective propagation delays of binary and m-valued ICs and the interconnection issue. We conclude with the challenges for m-valued circuits in the competition with the exponential performance increase of binary circuits.

Low-sensitivity digital filters are required for accurate signal processing. Among many low-sensitivity digital filters, a method using complex allpass circuits is well-known. In this paper, a new synthesis of complex allpass circuits is proposed. The proposed synthesis can be realized more easily either only in the z-domain or in the s-domain than conventional methods. The key concept for the synthesis is based on the factorization of lossless scattering matrices. Complex allpass circuits are interpreted as lossless digital two-port circuits, whose scattering matrices are factored. Furthermore, in the cases of Butterworth, Chebyshev and inverse Chebyshev responses, the explicit formulae for multiplier coefficients are derived, which enable us to synthesize the objective circuits directly from the specifications in the s-domain. Finally design examples verify the effectiveness of the proposed method.

An adder-based arithmetic VLSI processor using the SD number system is proposed for the applications of real-time computation such as intelligent robot system. Especially in the intelligent robot control system, not only high throughput but also small latency is a very important subject to make quick response for the sensor feedback situation, because the next input sample is obtained only after the robot actually moves. It is essential in the VLSI architecture for the intelligent robot system to make the latency as small as possible. The use of parallelism is an effective approach to reduce the latency. To meet the requirement, an architecture of a new multiple-valued arithmetic VLSI processor is developed. In the processor, addition and subtraction are performed by using the single adderbased processing element (PE). More complex basic arithmetic operations such as multiplication and division are performed by the appropriate data communications between the adder-based PEs with preserving their parallelism. In the proposed architecture, fine-grain parallel processing at the adder-based PE level is realized, and all the PEs can be fully utilized for any parallel arithmetic operations according to adder-based data dependency graph. As a result, the processing speed will be greatly increased in comparison with the conventional parallel processors having the different kinds of the arithmetic PEs such as an adder, a multiplier and a divider. To realize the arithmetic VLSI processor using the adder-based PEs, we introduce the signed-digit (SD) number system for the parallel arithmetic operations because the SD arithmetic has the advantage of modularity as well as parallelism. The multiple-valued bidirectional currentmode technology is also used for the implementation of the compact and high-speed adder-based PE, and the reduction of the number of the interconnections. It is demonstrated that these advantges of the multiple-valued technology are fully used for the implementation of the arithmetic VLSI processor. As a result, the latency of the proposed multiple-valued processor is reduced to 25% that of the binary processor integrated in the same chip size.

Future broadband ATM networks are expected to accommodate various kinds of multi-media services with different traffic characteristics and quality of service (QOS) requirements. However, it is very difficult to control traffic by conventional mechanisms in this complex traffic environment. As an alternative approach, a multilayer perceptron neural network model is proposed as an intelligent control mechanism like "a traffic control policeman" in order to perform ATM connection admission control. This proposed neural control model is analyzed by computer simulations in a homogeneous and heterogeneous traffic environment and the result shows the effectiveness of this intelligent control mechanism, compared with that of an analytical method.

Rapid advances in integrated circuit technology based on binary logic have made possible the fabrication of digital circuits or digital VLSI systems with not only a very large number of devices on a single chip or wafer, but also high-speed processing capability. However, the advance of processing speeds and improvement in cost/performance ratio based on conventional binary logic will not always continue unabated in submicron geometry. Submicron integrated circuits can handle multiple-valued signals at high speed rather than binary signals, especially at data communication level because of the reduced interconnections. The use of nonbinary logic or discrete-analog signal processing will not be out of the question if the multiple-valued hardware algorithms are developed for fast parallel operations. Moreover, in VLSI or ULSI processors the delay time due to global communications between functional modules or chips instead of each functional module itself is the most important factors to determine the total performance. Locally computable hardware implementation and new parallel hardware algorithms natural to multiple-valued data representation and circuit technologies are the key properties to develop VLSI processors in submicron geometry. As a result, multiple-valued VLSI processors make it possible to improve the effective chip density together with the processing speed significantly. In this paper, we summarize several potential advantages of multiple-valued VLSI processors in submicron geometry due to great reduction of interconnection and due to the suitability to locally computable hardware implementation, and demonstrate that some examples of special-purpose multiple-valued VLSI processors, which are a signed-digit arithmetic VLSI processor, a residue arithmetic VLSI processor and a matching VLSI processor can achieve higher performance for real-world computing system.

A method is proposed for realizing any k-valued n-variable function with a celluler array, which consists of linear arrays (called input arrays) and a rectangular array (called control array). In this method, a k-valued n-variable function is divided into kn-1 one-variable functions and remaining (n1)-variable function. The parts of one-variable functions are realized by the input arrays, remaintng the (n1)-variable function is realized by the control array. The array realizing the function is composed by connecting the input arrays with the control array. Then, this array requires (kn2)kn-1 cells and the number is smaller than the other rectangular arrays. Next, a ternary cell circuit and a literal circuit are actually constructed with CMOS transistors and NMOS pass transistors. The experiment shows that these circuits perform the expected operations.

A technique is presented for constructing (d,k) block codes capable of detecting single bit errors and single peak-shift errors in consecutive two runs. This constrains the runlengths in the code sequences to odd numbers. The capacities and the cardinalities for finite code length of these codes are described. A technique is also proposed for constructing (d,k) block codes capable of correcting single peak-shift errors.

We have developed a new functional MOS transistor called Neuron MOSFET (abbreviated as neuMOS or νMOS) which simulates the function of biological neurons. The new transistor is capable of executing a weighted sum calculation of multiple input signals and threshold operation based on the result of weighted summation, all in the voltage mode at a single transistor level. By utilizing its neuron-like very powerful functional capability, various circuits essential for multiple-valued logic operation have been designed using quite simple circuit configurations. The circuit designs for data conversion between the multivalued and binary logic systems and for generating universal literal functions are described and their experimental verifications are presented. One of the most important features of νMOS multivalued lagic circuit is that the circuit operates basically in the voltage mode, thus greatly reducing the power dissipation as compared to the conventional current mode circuitry. This is indeed most essential in implementing multivalued logic systems in ultra large scale integration. Another important feature of νMOS design is in its flexibility of implementing logic functions. The functional form of a universal literal function, for instance, can be arbitrarily altered by external signals without any modifications in its hardware configuration. A circuit representing multiple-valued multithreshold functions is also proposed.

Broadband ISDN based on ATM technologies is expected to offer enhanced and sophisticated services to customers. Since ATM will first be introduced in the business communication world, it will be worth to discuss the future image of desirable ATM customer premises network (CPN). In this paper, we first consider the possible migration scenario of Broadband CPN and some important requirements for the realization of the scenario. Then, we discuss the key issues to be solved for future ATM-CPN, which include network topology, traffic control and connectionless communication services.

The properties of the Haar Transform (HT) are discussed based on the Wavelet Transform theory. A system with two channels at resolution 2-1 and 2-2 for detecting paroxysm-spike in human's EEG is presented according to the multiresolution properties of the HT. The system adopts a coarse-to-fine strategy. First, it performs the coarse recognition on the 2-2 channel for selecting the candidate of spike in terms of rather relaxed criterion. Then, if the candidate appears, the fine recognition on the 2-1 channel is carried out for detecting spike in terms of stricter criterion. Three features of spike are extracted by investigating its intrinsic properties based on the HT. In the case of having no knowledge of prior probability of the presence of spike, the Neyman-Pearson criteria is applied to determining thresholds on the basis of the probability distribution of background and spike obtained by the results of statistical analysis to minimize error probability. The HT coefficients at resolution 2-2 and 2-1 can be computed individually and the data are compressed with 4:1 and 2:1 respectively. A half wave is regarded as the basic recognition unit so as to be capable of detecting negative and positive spikes simultaneously. The system provides a means of pattern recognition for non-stationary signal including sharp variation points in the transform domain. It is specially suitable and efficient to recognize the transient wave with small probability of occurrence in non-stationary signal. The practical examples show the performance of the system.

Widespread penetration of data communications in a LAN environment is generating a demand for high speed data transfer over wide area networks. It is anticipated that the connectionless (CL) service based on IEEE802.6 technology, called Switched Multi-megabit Data Service (SMDS), will be employed before this is realized by B-ISDN based technology. An important early application of B-ISDN will be interconnections between LANs, and continued support of the IEEE802.6 based CL service. This paper first reviews relevant technologies, clarifies comparison between IEEE802.6 based and B-ISDN based CL services, and points out that the important feature for users is that both CL services conform to the E.164 ISDN numbering plan for message addressing. Since an addressing scheme is the key to network services, conformity between the two will easily rationalize service migration from the IEEE802.6 based CL service to the B-ISDN based CL service. To permit such a service migration, this paper considers interworking scenarios for two CL services taking account of the penetration of inter-LAN communications. An exploring path is also presented to that users will not need to be aware of an alternation of network configuration, and smooth migration can take place. For facilitating high volume CL communications in the B-ISDN era, a virtual CL network is discussed to utilize ATM functionalities and to realize broadcasting and robust connectionless service capabilities. An overall comparison between a ring and mesh/star topology for the CL network is presented, and a detailed performance study is addressed in the context of Quality of Service which may depend on the particular application. This paper then describes a connectionless switch architecture in which a message switch combined with an ATM cell channel switch is presented. One scheme which receives specific attention here is a non-assembly message switching method to achieve robust switching capabilities. Typical performance evaluation results based on an M/G/1 queueing model are also reported.

Broadband multimedia information environments are part of the next big advance in communications and computer technology. The use of multimedia infrastructures in offices is becoming very important. This paper deals with a service concept and human interfaces based on a paper metaphor. The proposed service offers the advantages of paper and eliminates the disadvantages. The power of multimedia's expressiveness, user interaction, and hypermedia technology are key points of our solution. We propose a system configuration for implementing the service/human interface.

In this paper, we study the performance of convolutional coding using an error-and-erasure correction Viterbi decoder for π/4-shift QDPSK mobile radio transmission. The receiver uses received signal envelope as channel state information to erase unreliable symbols instead of making explicit decision before decoding. The performance study is carried out over frequency-selective fading channel with additive white Gaussian noise, co-channel interference and propagation delay spread. The results show that decoding with symbol erasure can significantly improve the system transmission performance compared to decoding without symbol erasure.

Real-time database systems have the properties of database and real-time systems. This means they must keep timing constraints of transactions as required in real-time systems, and at the same time ensure database consistency as required in database systems. Real-time concurrency control is a general approach for resolving this conflict. In this type of control, a concurrency control technique for database systems is integrated with a task scheduling technique for real-time systems. This paper surveys previous studies on real-time concurrency control and considers future research directions.

An information retrieval system based on a dynamic thesaurus was developed utilizing the connectionist approach. The dynamic thesaurus consists of nodes, which represent each term of a thesaurus, and links, which represent the connections between nodes. Term information that is automatically extracted from user's relevant documents is used to change node weights and generate links. Thus, node weights and links reflect a user's interest. A document retrieval experiment using the dynamic thesaurus was conducted in which both a high recall rate and a high precision rate were achieved.