This paper expands Bartlett's bisection theorem. The theory of modal S-parameters and their circuit representation is constructed from a group-theoretic perspective. Criteria for the division of a circuit at a fixed node whose state is distinguished by the irreducible representation of its stabilizer subgroup are obtained, after being inductively introduced using simple circuits as examples. Because these criteria use only circuit symmetry and do not require human judgment, the distinction is reliable and implementable in a computer. With this knowledge, the entire circuit can be characterized by a finite combination of smaller circuits. Reducing the complexity of symmetric circuits contributes to improved insights into their characterization, and to savings of time and effort in calculations when applied to large-scale circuits. A three-phase filter and a branch-line coupler are analyzed as application examples of circuit and electromagnetic field analysis, respectively.

This paper presents a system for the automatic generation of Galois-field (GF) arithmetic circuits, named the GF Arithmetic Module Generator (GF-AMG). The proposed system employs a graph-based circuit description called the GF Arithmetic Circuit Graph (GF-ACG). First, we present an extension of the GF-ACG to handle GF(pm) (p≥3) arithmetic circuits, which can be efficiently implemented by multiple-valued logic circuits in addition to the conventional binary circuits. We then show the validity of the generation system through the experimental design of GF(pm) multipliers for different p-values. In addition, we evaluate the performance of three types of GF(2m) multipliers and typical GF(pm) multipliers (p≥3) empirically generated by our system. We confirm from the results that the proposed system can generate a variety of GF parallel multipliers, including practical multipliers over GF(pm) having extension degrees greater than 128.

The Internet of Things (IoT) is defined as a global infrastructure for the Information Society, enabling advanced services by interconnecting (physical and virtual) things based on, existing and evolving, interoperable information and communication technologies by ITU-T. Data may be communicated in low-power and lossy environments, which causes complicated security issues. Furthermore, concerns are raised over access of personally identifiable information pertaining to IoT devices, network and platforms. Security and privacy concerns have been main barriers to implement IoT, which needs to be resolved appropriate security and privacy measures. This paper describes security threats and privacy concerns of IoT, surveys current studies related to IoT and identifies the various requirements and solutions to address these security threats and privacy concerns. In addition, this paper also focuses on major global standardization activities for security and privacy of Internet of Things. Furthermore, future directions and strategies of international standardization for theInternet of Thing's security and privacy issues will be given. This paper provides guidelines to assist in suggesting the development and standardization strategies forward to allow a massive deployment of IoT systems in real world.

In the topologies for interconnected nodes, it is desirable to have a low degree and a small diameter. For the same number of nodes, a dual-cube topology has almost half the degree compared to a hypercube while increasing the diameter by just one. Hence, it is a promising topology for interconnection networks of massively parallel systems. We propose here a stochastic fault-tolerant routing algorithm to find a non-faulty path from a source node to a destination node in a dual-cube.

This paper presents FIR digital filters based on stochastic/binary hybrid computation with reduced hardware complexity and high computational accuracy. Recently, some attempts have been made to apply stochastic computation to realization of digital filters. Such realization methods lead to significant reduction of hardware complexity over the conventional filter realizations based on binary computation. However, the stochastic digital filters suffer from lower computational accuracy than the digital filters based on binary computation because of the random error fluctuations that are generated in stochastic bit streams, stochastic multipliers, and stochastic adders. This becomes a serious problem in the case of FIR filter realizations compared with the IIR counterparts because FIR filters usually require larger number of multiplications and additions than IIR filters. To improve the computational accuracy, this paper presents a stochastic/binary hybrid realization, where multipliers are realized using stochastic computation but adders are realized using binary computation. In addition, a coefficient-scaling technique is proposed to further improve the computational accuracy of stochastic FIR filters. Furthermore, the transposed structure is applied to the FIR filter realization, leading to reduction of hardware complexity. Evaluation results demonstrate that our method achieves at most 40dB improvement in minimum stopband attenuation compared with the conventional pure stochastic design.

We developed a novel, proof-of-concept side-channel attack framework called RouteDetector, which identifies a route for a train trip by simply reading smart device sensors: an accelerometer, magnetometer, and gyroscope. All these sensors are commonly used by many apps without requiring any permissions. The key technical components of RouteDetector can be summarized as follows. First, by applying a machine-learning technique to the data collected from sensors, RouteDetector detects the activity of a user, i.e., “walking,” “in moving vehicle,” or “other.” Next, it extracts departure/arrival times of vehicles from the sequence of the detected human activities. Finally, by correlating the detected departure/arrival times of the vehicle with timetables/route maps collected from all the railway companies in the rider's country, it identifies potential routes that can be used for a trip. We demonstrate that the strategy is feasible through field experiments and extensive simulation experiments using timetables and route maps for 9,090 railway stations of 172 railway companies.

Distributed Denial of Service (DDoS) attacks based on HTTP and HTTPS (i.e., HTTP(S)-DDoS) are increasingly popular among attackers. Overlay-based mitigation solutions attract small and medium-sized enterprises mainly for their low cost and high scalability. However, conventional overlay-based solutions assume content inspection to remotely mitigate HTTP(S)-DDoS attacks, prompting trust concerns. This paper reports on a new overlay-based method which practically adds a third level of client identification (to conventional per-IP and per-connection). This enhanced identification enables remote mitigation of more complex HTTP(S)-DDoS categories without content inspection. A novel behavior-based reputation and penalty system is designed, then a simplified proof of concept prototype is implemented and deployed on DeterLab. Among several conducted experiments, two are presented in this paper representing a single-vector and a multi-vector complex HTTP(S)-DDoS attack scenarios (utilizing LOIC, Slowloris, and a custom-built attack tool for HTTPS-DDoS). Results show nearly 99.2% reduction in attack traffic and 100% chance of legitimate service. Yet, attack reduction decreases, and cost in service time (of a specified file) rises, temporarily during an approximately 2 minutes mitigation time. Collateral damage to non-attacking clients sharing an attack IP is measured in terms of a temporary extra service time. Only the added identification level was utilized for mitigation, while future work includes incorporating all three levels to mitigate switching and multi-request per connection attack categories.

Android is one of the most popular mobile device platforms. However, since Android apps can be disassembled easily, attackers inject additional advertisements or malicious codes to the original apps and redistribute them. There are a non-negligible number of such repackaged apps. We generally call those malicious repackaged apps “clones.” However, there are apps that are not clones but are similar to each other. We call such apps “relatives.” In this work, we developed a framework called APPraiser that extracts similar apps and classifies them into clones and relatives from the large dataset. We used the APPraiser framework to study over 1.3 million apps collected from both official and third-party marketplaces. Our extensive analysis revealed the following findings: In the official marketplace, 79% of similar apps were attributed to relatives, while in the third-party marketplace, 50% of similar apps were attributed to clones. The majority of relatives are apps developed by prolific developers in both marketplaces. We also found that in the third-party market, of the clones that were originally published in the official market, 76% of them are malware.

The Möbius cube is a variant of the hypercube. Its advantage is that it can connect the same number of nodes as a hypercube but with almost half the diameter of the hypercube. We propose an algorithm to solve the node-to-node disjoint paths problem in n-Möbius cubes in polynomial-order time of n. We provide a proof of correctness of the algorithm and estimate that the time complexity is O(n2) and the maximum path length is 3n-5.

This work develops a third-order multibit switched-current (SI) delta-sigma modulator (DSM) with a four-bit switched-capacitor (SC) flash analog-to-digital converter (ADC) and an incremental data weighted averaging circuit (IDWA), which is fabricated using 0.18µm 1P6M CMOS technology. In the proposed DSM, a 4-bit SC flash ADC is used to improve its resolution, and an IDWA is used to reduce the nonlinearity of digital-to-analog converter (DAC) by moving the quantization noise out of the signal band by first-order noise shaping. Additionally, the proposed differential sample-and-hold circuit (SH) exhibits low input impedance with feedback and width-length adjustment in the SI feedback memory cell (FMC) to increase the conversion rate. A coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate for the mirror error that is caused by the current mirror. Measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption, and chip area are 64.1 dB, 64.4 dB, 10.36 bits, 18.82 mW, and 0.45 × 0.67 mm2 (without I/O pad), respectively, with a bandwidth of 20 kHz, an oversampling ratio (OSR) of 256, a sampling frequency of 10.24 MHz, and a supply voltage of 1.8 V.

This paper presents an automatic hierarchical formal verification method for arithmetic circuits over Galois fields (GFs) which are dedicated digital circuits for GF arithmetic operations used in cryptographic processors. The proposed verification method is based on a combination of a word-level computer algebra procedure with a bit-level PPRM (Positive Polarity Reed-Muller) expansion procedure. While the application of the proposed verification method is not limited to cryptographic processors, these processors are our important targets because complicated implementation techniques, such as field conversions, are frequently used for side-channel resistant, compact and low power design. In the proposed method, the correctness of entire datapath is verified over GF(2m) level, or word-level. A datapath implementation is represented hierarchically as a set of components' functional descriptions over GF(2m) and their wiring connections. We verify that the implementation satisfies a given total-functional specification over GF(2m), by using an automatic algebraic method based on the Gröbner basis and a polynomial reduction. Then, in order to verify whether each component circuit is correctly implemented by combination of GF(2) operations, i.e. logic gates in bit-level, we use our fast PPRM expansion procedure which is customized for handling large-scale Boolean expressions with many variables. We have applied the proposed method to a complicated AES (Advanced Encryption Standard) circuit with a masking countermeasure against side-channel attack. The results show that the proposed method can verify such practical circuit automatically within 4 minutes, while any single conventional verification methods fail within a day or even more.

We propose an architecture for a 1-bit band-pass delta-sigma modulator (BP-DSM) that outputs concurrent multiband RF signals. The proposed BP-DSM consists of parallel bandpass filters (BPFs) in the feedback loop to suppress the quantization noise at each target frequency band while maintaining the stability. Each BPF is based on second-order parallel infinite impulse response (IIR) filters. This architecture can unify and reconfigure the split BPFs according to the number of bands. The architecture complexity is proportional to the bandwidth of each RF signal and is independent of the carrier spacing between the bands. The conventional architecture of a concurrent multiband digital modulator, reported previously, has multiple input ports to the dedicated BPF at each band and so it cannot be efficiently integrated. Measurements show that the proposed architecture is feasible for transmitting a concurrent dual-band and a triple-band by changing the 1-bit digital data stream while keeping a data transmission rate of 10Gb/s. We demonstrate that the proposed architecture outputs the signal with LTE intra-band and inter-band carrier aggregation on 0.8GHz, 2.1GHz and 3.5GHz, each with 40MHz bandwidth in 120MHz aggregated bandwidth, whose bandwidth surpasses the bandwidth with carrier aggregation of LTE-A up to 100MHz. Adjacent channel leakage ratios of -49dBc and -46dBc are achieved at 3.5GHz in the concurrent dual-band and triple-band, respectively.

This paper proposes 0-1-A-Ā LUT, a new programmable logic using atom switches, and a delay-optimal mapping algorithm for it. Atom switch is a non-volatile memory device of very small geometry which is fabricated between metal layers of a VLSI, and it can be used as a switch device of very small on-resistance and parasitic capacitance. While considerable area reduction of Look Up Tables (LUTs) used in conventional Field Programmable Gate Arrays (FPGAs) has been achieved by simply replacing each SRAM element with a memory element using a pair of atom switches, our 0-1-A-Ā LUT achieves further area and delay reduction. Unlike the conventional atom-switch-based LUT in which all k input signals are fed to a MUX, one of input signals is fed to the switch array, resulting area reduction due to the reduced number of inputs of the MUX from 2k to 2k-1, as well as delay reduction due to reduced fanout load of the input buffers. Since the fanout of this input buffers depends on the mapped logic function, this paper also proposes technology mapping algorithms to select logic function of fewer number of fanouts of input buffers to achieve further delay reduction. From our experiments, the circuit delay using our k-LUT is 0.94% smaller in the best case compared with using the conventional atom-switch-based k-LUT.

This paper explores the potential of orbital angular momentum (OAM) multiplexing as a means to enable high-speed wireless transmission. OAM is a physical property of electro-magnetic waves that are characterized by a helical phase front in the propagation direction. Since the characteristic can be used to create multiple orthogonal channels, wireless transmission using OAM can enhance the wireless transmission rate. Comparisons with other wireless transmission technologies clarify that OAM multiplexing is particularly promising for point-to-point wireless transmission. We also clarify three major issues in OAM multiplexing: beam divergence, mode-dependent performance degradation, and reception (Rx) signal-to-noise-ratio (SNR) reduction. To mitigate mode-dependent performance degradation we first present a simple but practical Rx antenna design method. Exploiting the fact that there are specific location sets with phase differences of 90 or 180 degrees, the method allows each OAM mode to be received at its high SNR region. We also introduce two methods to address the Rx SNR reduction issue by exploiting the property of a Gaussian beam generated by multiple uniform circular arrays and by using a dielectric lens antenna. We confirm the feasibility of OAM multiplexing in a proof of concept experiment at 5.2 GHz. The effectiveness of the proposed Rx antenna design method is validated by computer simulations that use experimentally measured values. The two new Rx SNR enhancement methods are validated by computer simulations using wireless transmission at 60 GHz.

This letter proposes a heuristic algorithm to select check variables, which are points of comparison for error detection, for soft-error tolerant datapaths. Our soft-error tolerance scheme is based on check-and-retry computation and an efficient resource management named speculative resource sharing (SRS). Starting with the smallest set of check variables, the proposed algorithm repeats to add new check variable one by one incrementally and find the minimum latency solution among the series of generated solutions. During the process, each new check variable is selected so that the opportunity of SRS is enlarged. Experimental results show that improvements in latency are achieved compared with the choice of the smallest set of check variables.

This paper discusses the use of a common computer mouse as a pointing interface for tabletop displays. In the use of a common computer mouse for tabletop displays, there might be an angular distance between the screen coordinates and the mouse control coordinates. To align those coordinates, this paper introduces a screen coordinates calibration technique using a shadow cursor. A shadow cursor is the basic idea of manipulating a mouse cursor without any visual feedbacks. The shadow cursor plays an important role in obtaining the angular distance between the two coordinates. It enables the user to perform a simple mouse manipulation so that screen coordinates calibration will be completed in less than a second.

A novel real-valued ESPRIT (RV-ESPRIT) algorithm is proposed to estimate the direction of arrival (DOA) and direction of departure (DOD) for noncircular signals in bistatic MIMO radar. By exploiting the property of signal noncircularity and Euler's formula, a new virtual array data of bistatic MIMO radar, which is twice that of the MIMO virtual array data, is established with real-valued sine and cosine data. Then the receiving/transmitting selective matrices are constructed to obtain the receiving/transmitting rotationally invariant factors. Compared to the existing angle estimation methods, the proposed algorithm has lower computational load. Simulation results confirm the effectiveness of the RV-ESPRIT.

We investigate a finite-sized self-complementary bow-tie antenna (SC-BTA) integrated with a semiconductor mesa with respect to radiation characteristics such as the peak radiation frequency and bandwidth around the fundamental radiation mode. For this investigation, we utilize an equivalent circuit model of the SC-BTA derived in our previous work and a finite element method solver. Moreover, we derive design guidelines for the radiation characteristics in the form of size scaling-rules with respect to the antenna outer size for a terahertz transmitter.

High-resolution bio-imaging is a key component for the advancement of life science. CMOS electronics is one of the promising candidates for emerging high-resolution devices because it offers nano-scale transistors. However, the resolution of the existing CMOS bio-imaging devices is several micrometers, which is insufficient for analyzing small objects such as bacteria and viruses. This paper presents the results of an analysis of the scalability of a current-mode analog-to-time converter (CMATC) to develop a high-resolution CMOS biosensor array. Simulations were performed using 0.6-µm, 0.25-µm, and 0.065-µm CMOS technology nodes. The Simulation results for the power consumption and resolution (cell size) showed that the CMATC has high-scalability and is a promising candidate to enable high-resolution CMOS bio-imaging.

This study mainly involved examining a high-directivity radiation system with spherical dielectric resonator as pseudo multipole source. The method of spherical wave expansion is focused on wherein the plane wave that is infinitely spread can be radiated from or absorbed by multipoles at the origin. It is not possible to explain this phenomenon by Huygens' principle, which is a basic principle of aperture antenna theory. Thus, in the study, a high-directivity beam design is proposed by synthesizing spherical waves. The directivity of the synthesized spherical wave corresponds with the angular momentum and angle, which is an uncertainty relation different from that of the aperture source. The estimation of the effective aperture of the synthesized spherical wave indicates that the wave intrinsic source is assumed to exist at the surface of the cutoff region. Finally, the results reveal that a radiation system without a singular point can be composed using a spherical dielectric resonator. The study discusses the potential of a high-directivity radiation system constructed by a multi-mode degenerate spherical dielectric resonator as a pseudo multipole source.