In this paper, we present sub-1-V CMOS-based electrophoresis method for small-form-factor biomolecule manipulation that is contained in a microchip. This is the first time this type of device has been presented in the literature. By combining CMOS technology with electroless gold plating, the electrode pitch can be reduced and the required input voltage can be decreased to less than 1 V. We fabricated the CMOS electrophoresis chip in a cost-competitive 0.6 µm standard CMOS process. A sample/hold circuit in each cell is used to generate a constant output from an analog input. After forming gold electrodes using an electroless gold plating technique, we were able to manipulate red food coloring with a 0-0.7 V input voltage range. The results shows that the proposed CMOS chip is effective for electrophoresis-based manipulation.

60GHz wireless communication requires analog baseband circuits having a bandwidth of about 1GHz. This paper presents a wide bandwidth current-mode low pass filter technique which involves current amplifiers, resistors and capacitors. The proposed current-mode filter is obtained by replacing an integrator employing an op-amp with another integrator employing a current amplifier. With the low input impedance current amplifier having little variation of the input impedance, the proposed filter is expected to improve linearity and power efficiency. The proposed current amplifier which employs super source follower topology with complementary input is suitable for the filter because of its class AB operation. Although simulation results shows the conventional current amplifier which employs super source follower topology without the complementary input has 12Ω variation and 30Ω input impedance, the proposed current amplifier has 1Ω variation and 21Ω input impedance. A fourth order 1GHz bandwidth filter which involves the proposed current amplifiers is designed in a 65nm CMOS technology. The filter can achieve IIP3 of 1.3dBV and noise of 0.6mVrms with power consumption of 13mW under supply voltage of 1.2V according to simulation results with layout parasitic extraction models. Active area of the filter is 380μm×170μm.

This paper presents a thin, compact beacon transmitter operating without needing battery replacement by using a photovoltaic (PV) film harvester. The beacon is formed of a power-control circuit (PCC) that can monitor small amounts of power from the harvester and properly control mode switching at low-power consumption. This leads to the realization of a maintenance-free beacon requiring no battery replacement. The beacon prototype is 55×20×2 mm in size and has a PV cell of 3 cm2. It allows a start-up operation from just 44-lux illuminance. The PV area required for the operation can be 1.7 times smaller than that of conventional beacons, thanks to the current saving with appropriate sequential control of the PCC. Since the beacon makes operation possible in emergency stairs, underground passages and other dark places, the application field for Internet of things (IoT) services can be expanded. Furthermore, a beacon equipped with a secondary battery (BSB: Beacon with Secondary Battery) can be configured by adding a charge-discharge power monitoring circuit. The BSB transmits an advertising packet during the daytime while charging surplus power, and works using the stored power during the night; this results in a continuous operation for one week with one transmission every 3 seconds even at 0-lux illuminance. Without developing a new radiofrequency chip or module, commercial low-power devices can be easily adjusted depending on the application by adding appropriate power-control circuits. We are convinced that this design scheme will be effective as a rapid design proposal for IoT services.

The purpose of document modeling is to learn low-dimensional semantic representations of text accurately for Natural Language Processing tasks. In this paper, proposed is a novel attention-based hybrid neural network model, which would extract semantic features of text hierarchically. Concretely, our model adopts a bidirectional LSTM module with word-level attention to extract semantic information for each sentence in text and subsequently learns high level features via a dynamic convolution neural network module. Experimental results demonstrate that our proposed approach is effective and achieve better performance than conventional methods.

An online nonnegative matrix factorization (NMF) algorithm based on recursive least squares (RLS) is described in a matrix form, and a simplified algorithm for a low-complexity calculation is developed for frame-by-frame online audio source separation system. First, the online NMF algorithm based on the RLS method is described as solving the NMF problem recursively. Next, a simplified algorithm is developed to approximate the RLS-based online NMF algorithm with low complexity. The proposed algorithm is evaluated in terms of audio source separation, and the results show that the performance of the proposed algorithms are superior to that of the conventional online NMF algorithm with significantly reduced complexity.

An output voltage-current equation of charge pump DC-DC voltage multiplier using diodes is provided to cover wide clock frequency and output current ranges for designing energy harvester operating at a near-threshold voltage or in sub-threshold region. Equivalent circuits in slow and fast switching limits are extracted. The effective threshold voltage of the diode in slow switching limit is also derived as a function of electrical characteristics of the diodes, such as the saturation current and voltage slope parameter, and design parameters such as the number of stages, capacitance per stage, parasitic capacitance at the top plate of the main boosting capacitor, and the clock frequency. The model is verified compared with SPICE simulation.

Improving robustness in electrostatic discharge (ESD) protection by inserting drain-side isolated silicon-controlled rectifiers (SCRs) in a high-voltage (HV) p-channel lateral-diffused MOSFET (pLDMOS) device was investigated in this paper. Additionally, the effects of anti-ESD reliability in the HV pLDMOS transistors provided by this technique were evaluated. From the experimental data, it was determined that the holding voltage (Vh) values of the pLDMOS with an embedded npn-arranged SCR and discrete thin-oxide (OD) layout on the cathode side increased as the parasitic SCR OD row number decreased. Moreover, the trigger voltage (Vt1) and the Vh values of the pLDMOS with a parasitic pnp-arranged SCR and discrete OD layout on the drain side fluctuated slightly as the SCR OD-row number decreased. Furthermore, the secondary breakdown current (It2) values (i.e., the equivalent ESD-reliability robustness) of all pLDMOS-SCR npn-arranged types increased (>408.4%) to a higher degree than those of the pure pLDMOS, except for npn-DIS_3 and npn-DIS_2, which had low areas of SCRs. All pLDMOS-SCR pnp-arranged types exhibited an increase of up to 2.2A-2.4A, except for the pnp_DIS_3 and pnp_DIS_2 samples; the pnp_DIS_91 increased by approximately 2000.9% (249.1%), exhibiting a higher increase than that of the reference pLDMOS (i.e., the corresponding pnp-stripe type). The ESD robustness of the pLDMOS-SCR pnp-arranged type and npn-arranged type with a discrete OD layout on the SCR cathode side was greater than that of the corresponding pLDMOS-SCR stripe type and a pure pLDMOS, particularly in the pLDMOS-SCR pnp-arranged type.

Nowadays, vector map content is widely used in the areas of life, science and the military. Due to the fact that vector maps bring great value and that their production process is expensive, a large volume of vector map data is attacked, stolen and illegally distributed by pirates. Thus, vector map data must be encrypted before being stored and transmitted in order to ensure the access and to prevent illegal copying. This paper presents a novel perceptual encryption algorithm for ensuring the secured storage and transmission of vector map data. Polyline data of vector maps are extracted to interpolate a spline curve, which is represented by an interpolating vector, the curvature degree coefficients, and control points. The proposed algorithm is based on encrypting the control points of the spline curve in the frequency domain of discrete cosine transform. Control points are transformed and selectively encrypted in the frequency domain of discrete cosine transform. They are then used in an inverse interpolation to generate the encrypted vector map. Experimental results show that the entire vector map is altered after the encryption process, and the proposed algorithm is very effective for a large dataset of vector maps.

This paper focuses on differences in comment densities among individual programmers, and proposes to adjust the conventional code complexity metric (the cyclomatic complexity) by using the abnormality of the comment density. An empirical study with nine popular open source Java products (including 103,246 methods) shows that the proposed metric performs better than the conventional one in predicting change-prone methods; the proposed metric improves the area under the ROC curve (AUC) by about 3.4% on average.

High Efficiency Video Coding is a new video coding standard after H.264/AVC. By introducing a flexible coding unit, which can be recursively divided from 64×64 to 8×8 blocks in a Quadtree-Structure, HEVC achieves significantly higher coding efficiency than the previous standards. With the flexible CU structure, HEVC can effectively adapt to highly varying contents with a smaller CU or to flat contents with a larger CU, making it suitable for applications from mobile video to super high definition television. On the other hand, CU division does incur high computational cost for HEVC. In this paper, we propose a simple and fast CU division algorithm by using only a subset of pixels to determine when CU division happens. Experiment results show that our algorithm can achieve prediction quality close to HEVC Test Model with much lower computational cost.

In this paper, a nanopower supply-insensitive complementary metal-oxide-semiconductor (CMOS) unit threshold voltage (Vth) extractor circuit is proposed. It meets the contemporary industry demand for portable devices that operate with very low power consumption and small output sensitivity. An α times Vth (αVth) extractor is also described, in which α varies continuously. Both incremental and decremental αVth voltages are obtained. A post-layout simulation results using HSPICE with CMOS 0.18um process show that the proposed unit Vth extractor consumes 265nW of power given a 1.6V power supply. Sensitivity to temperature is 0.022%/°C ranging from 0°C to 100°C. Sensitivity to supply voltage is 0.027%/V.

The sub-blocking algorithm has been known as a core component in implementing a turbo decoder using a Graphic Processing Unit (GPU) to use as many cores in the GPU as possible for parallel processing. However, even though the sub-blocking algorithm allows a large number of threads in a given GPU to be adopted for processing a large number of sub-blocks in parallel, each thread must access the global memory with strided addresses, which results in uncoalesced memory access. Because uncoalesced memory access causes a lot of unnecessary memory transactions, the memory bandwidth efficiency drops significantly, possibly as low as 1/8 in the case of an Long Term Evolution (LTE) turbo decoder, depending upon the compute capability of a GPU. In this paper, we present a novel method for converting uncoalesced memory access into coalesced access in a way that completely recovers the memory bandwidth efficiency to 100% without additional overhead. Our experimental tests, performed with NVIDIA's Geforce GTX 780 Ti GPU, show that the proposed method can enhance the throughput by nearly 30% compared with a conventional turbo decoder that suffers from uncoalesced memory access. Throughput provided by the proposed method has been observed to be 51.4Mbps when the number of iterations and that of sub-blocks are set to 6 and 32, respectively, in our experimental tests, which far exceeds the performance of previous works implemented the Max-Log-MAP algorithm.

In general, tunnel diodes exhibit various types of oscillation mode: the sinusoidal mode or the nonsinusoidal mode which is known as the relaxation oscillation (RO) mode. We derive a condition for generating the RO in resonant tunneling diodes (RTDs) with essential components for equivalent circuit model. A conditional equation to obtain sufficient nonlinearity towards the robust RO is clarified. Moreover, its condition also can be applied in case of a bow-tie antenna integrated RTD, thus a design policy to utilize the RO region for the antenna integrated RTD is established by numerical evaluations of time-domain large-signal nonlinear analysis towards a terahertz transmitter for broadband wireless communications.

We propose a wideband reconfigurable circular-polarized single-port antenna to realize high-density linear integration for use in ground penetrating radars. We switch PIN diodes at a T-shaped probe to change its polarization. The forward- and reverse-biased probes work in cooperation to generate circular polarization. Experiments demonstrate the working bandwidths of 20.0% and 18.6% in the left- and right-hand polarization states, respectively, with 7.2 GHz center frequency. They are wider than those of conventional reconfigurable single-port circular-polarized antennas.

The performance of devices based on two dimensional (2D) materials is significantly affected upon prolonged exposure to atmosphere. We analyzed time based environmental degradation of electrical properties of HfS2 field effect transistors. Atmospheric entities like oxygen and moisture adversely affect the device surface and reduction in drain current is observed over period of 48 hours. Two corrective measures, namely, PMMA passivation and vacuum annealing, have been studied to address the diminution of current by contaminants. PMMA passivation prevents the device from environment and reduces the effect of Coulomb scattering. Improvement in current characteristics signifies the importance of dielectric passivation for 2D materials. On the other hand, vacuum annealing is useful in removing contaminants from the affected surface. In order to figure out optimum process conditions, properties have been studied at various annealing temperatures. The improvement in drain current level was observed upon vacuum annealing within optimum range of annealing temperature.

A high-image-rejection wireless receiver with an N-phase active RC complex filter is proposed and analyzed. Signal analysis shows that the double-conversion receiver with (N+N2) mixers corrects the gain and phase mismatches of the adjacent image. Monte Carlo simulations evaluate the relation between image-rejection performances and the dispersions of device parameters for the double-conversion wireless receiver. The Monte Carlo simulations show that the image rejection ratio of the adjacent image depends almost only on R and C mismatches in the complex filter.

Using a matrix approach based on a Markov process, we investigate the reliability of a circular connected-(1,2)-or-(2,1)-out-of-(m,n):F lattice system for the i.i.d. case. We develop a modified linear lattice system that is equivalent to this circular system, and propose a methodology that allows the systematic calculation of the reliability. It is based on ideas presented by Fu and Hu [6]. A partial transition probability matrix is used to reduce the computational complexity of the calculations, and closed formulas are derived for special cases.

Recurrent neural networks (RNNs) are a powerful model for sequential data. RNNs that use long short-term memory (LSTM) cells have proven effective in handwriting recognition, language modeling, speech recognition, and language comprehension tasks. In this study, we propose LSTM conditional random fields (LSTM-CRF); it is an LSTM-based RNN model that uses output-label dependencies with transition features and a CRF-like sequence-level objective function. We also propose variations to the LSTM-CRF model using a gate recurrent unit (GRU) and structurally constrained recurrent network (SCRN). Empirical results reveal that our proposed models attain state-of-the-art performance for named entity recognition.

The quality assessment of screen content images (SCIs) has been attractive recently. Different from natural images, SCI is usually a mixture of picture and text. Traditional quality metrics are mainly designed for natural images, which do not fit well into the SCIs. Motivated by this, this letter presents a simple and effective method to naturalize SCIs, so that the traditional quality models can be applied for SCI quality prediction. Specifically, bicubic interpolation-based up-sampling is proposed to achieve this goal. Extensive experiments and comparisons demonstrate the effectiveness of the proposed method.

A comprehensive model is presented for estimating the bit error rate (BER) of write disturbance in a resistive memory composed of a cross-point array. While writing a datum into the selected address, the non-selected addresses are biased by word-line (WL) and bit-line (BL). The stored datum in the non-selected addresses will be disturbed if the bias is large enough. It is necessary for the current flowing through the non-selected address to be calculated in order to estimate the BER of the write disturbance. Since it takes a long time to calculate the current flowing in a large-scale cross-point array, several simplified circuits have been utilized to decrease the calculating time. However, these simplified circuits are available to the selected address, not to the non-selected one. In this paper, new simplified circuits are proposed for calculating the current flowing through the non-selected address. The proposed and the conventional simplified circuits are used, and on that basis the trade-off between the write disturbance and the write error is discussed. Furthermore, the error correcting code (ECC) is introduced to improve the trade-off and to provide the low-cost memory chip matching current production lines.