Low noise terahertz (THz) receivers based on superconducting niobium nitride (NbN) hot electron bolometer (HEB) mixers have been designed, fabricated and measured for applications in astronomy and cosmology. The NbN HEB mixer consists of a planar antenna and an NbN bridge connecting across the antenna's inner terminals on a high-resistivity Si substrate. To eliminate the influence of direct detection and instability of the local oscillation (LO) power, a wire grid has been used to change the input LO power for compensating the shift of bias current during Y-factor measurement. The double sideband (DSB) receiver noise temperatures at 4.2 K without corrections have been measured from 0.65 to 3.1 THz. The excess quantum noise factor β of about 4 has been obtained, which agrees well with the calculated value. Allan variance of the HEB has been characterized, and Allan time TA longer than 0.4 s is obtained. We also estimated the temperature resolution of the HEB from the Allan variance and obtained the minimum temperature resolution of 1.1 K using a Gunn oscillator with its multipliers at 0.65 THz as an LO source.

Atmospheric radio ducts can trap VHF/UHF radio waves and propagate them over long distances. 284.4625 MHz Japanese radio wave signal measurements show that the radio waves are propagated to Korea coastal regions when ground temperatures exceed 10C. This paper discusses the reasons for the existence of this critical temperature threshold.

This paper investigates whether the self-heating effect in short intra-block wires will become apparent with technology scaling. These wires seem to have good thermal radiation characteristics, but we validate that the self-heating effect in local signal wires will be greater than that in optimal repeater-inserted global wires. Our numerical experiment shows that the maximum temperature increase from the silicon junction temperature will reach 40.4 in a steady state at a 14-nm process. Our attribution analysis also demonstrates that miniaturizing the area of wire cross-section exacerbates self-heating as well as using low-κ material and increased power dissipation in advanced technologies below 28 nm. It is revealed that the impact of self-heating on performance in local wires is limited, while underestimating the temperature may cause an unexpected reliability failure.

This paper evaluates impact of self-heating in wire interconnection on signal propagation delay in an upcoming 32 nm process technology, using practical physical parameters. This paper examines a 64-bit data transmission model as one of the most heating cases. Experimental results show that the maximum wire temperature increase due to the self-heating appears in the case where the ratio of interconnect delay becomes largest compared to the driver delay. However, even in the most significant case which induces the maximum temperature rise of 11.0, the corresponding increase in the wire resistance is 1.99% and the resulting delay increase is only 1.15%, as for the assumed 32 nm process. A part of the impact reduction of wire self-heating on timing comes from the size-effect of nano-scale wires.

In this paper, a motion field representation algorithm based on directional edge information has been developed. This work is aiming at building an ego-motion detection system using dedicated VLSI chips developed for real time motion field generation at low powers . Directional edge maps are utilized instead of original gray-scale images to represent local features of an image and to detect the local motion component in a moving image sequence. Motion detection by edge histogram matching has drastically reduced the computational cost of block matching, while achieving a robust performance of the ego-motion detection system under dynamic illumination variation. Two kinds of feature vectors, the global motion vector and the component distribution vectors, are generated from a motion field at two different scales and perspectives. They are jointly utilized in the hierarchical classification scheme employing multiple-clue matching. As a result, the problems of motion ambiguity as well as motion field distortion caused by camera shaking during video capture have been resolved. The performance of the ego-motion detection system was evaluated under various circumstances, and the effectiveness of this work has been verified.

High temperature adversely impacts on circuit's reliability, performance, and leakage power. During behavioral synthesis, both resource usage allocation and resource binding influence thermal profile. Current thermal-aware behavioral syntheses do not utilize location information of resources from floorplan and in addition only focus on binding, ignoring allocation. This paper proposes thermal-aware behavioral synthesis with resource usage allocation. Based on a hybrid metric of physical location information and temperature, we rebind operations and reallocate the number of resources under area constraint. Our approach effectively controls peak temperature and creates even power densities among resources of different types and within resources of the same type. Experimental results show an average of 8.6 drop in peak temperature and 5.3% saving of total power consumption with little latency overhead.

Block truncation coding (BTC) is an efficient image compression algorithm that generates a constant output bit-rate. For color image compression, vector quantization (VQ) is exploited to improve the coding efficiency. In this letter, we propose an improved VQ based BTC (VQ-BTC) algorithm using template matching and Lloyd quantization (LQ). The experimental results show that the proposed method improves the PSNR by 0.9 dB in average compared to the conventional VQ-BTC algorithms.

On the use of a surveillance camera, there is a case where privacy protection should be considered. This paper proposes a new privacy protection method by automatically degrading the face region in surveillance images. The proposed method consists of ROI coding of JPEG2000 and a face detection method based on template matching. The experimental result shows that the face region can be detected and hidden correctly.

The algebra of communicating shared resources (ACSR) is a timed process algebra which extends classical process algebras with the notion of a resource. In analyzing ACSR models, the existing techniques such as bisimulation checking and Hennessy-Milner Logic (HML) model checking are very important in theory of ACSR, but they are difficult to use for large complex system models in practice. In this paper, we suggest a framework to verify ACSR models against their requirements described in an expressive timed temporal logic. We demonstrate the usefulness of our approach with a real world case study.

Workflow nets (WF-nets) are Petri nets which represent workflows. Soundness is a criterion of logical correctness defined for WF-nets. It is known that soundness verification is intractable. In this paper, we propose a method to verify soundness using a Linear Temporal Logic (LTL) model checking tool, SPIN. We give an LTL necessary and sufficient condition to verify soundness for WF-nets without livelock. Acyclic WF-nets have no livelock, but cyclic WF-nets may have livelock. We also give a necessary and sufficient condition to verify livelock. Meanwhile, we show that any LTL model checking tool cannot verify soundness for WF-nets with livelock. We give necessary conditions to verify soundness for them. Those conditions enable us to use SPIN even if a given WF-net has livelock. We also develop a tool to verify soundness based on our method. We show effectiveness of our method by comparing our tool with existing soundness verification tools on verification time for 200 cyclic ACWF-nets.

Compiler is the most important supporting tool to facilitate the use of reconfigurable computing architecture (RCA). In this paper, a template-based compiler framework is proposed. This compiler can synthesize the executables for RCA from native high-level programming language source code directly. It supports to generate run-time dynamic configuration context. And it is capable to generate both full configuration context and partial configuration context. Experimental results show that the executables generated by the proposed compiler can achieve better execution performance and smaller configuration context size than previous compilers. Moreover, this compiler does not require the programmer to have any extra knowledge about the hardware architecture of RCA.

In this paper, first the temperature distribution of the pyramidal EM-wave absorber is calculated in the coupled method. Next, the injected power to the EM-wave absorber is changed to estimate the maximum power density that the EM-wave absorber can resist. As a result, the limitation of the injecting power density to a pyramidal EM-wave absorber is achievable.

It is known that the schedulability of a non-preemptive task set with fixed priority can be determined in pseudo-polynomial time. However, since Rate Monotonic scheduling is not optimal for non-preemptive scheduling, the applicability of existing polynomial time tests that provide sufficient schedulability conditions, such as Liu and Layland's bound, is limited. This letter proposes a new sufficient condition for non-preemptive fixed priority scheduling that can be used for any fixed priority assignment scheme. It is also shown that the proposed schedulability test has a tighter utilization bound than existing test methods.

Despite the prevalence of Java workloads across a variety of processor architectures, there is very little published data on the impact of the various processor design decisions on Java performance. We attribute the lack of data to the large design space resulting from the complexity of the modern superscalar processor and the additional complexities associated with executing Java bytecode using a virtual machine. To address this shortcoming, we use a statistically rigorous methodology to systematically quantify the the impact of the various processor microarchitecture parameters on Java execution performance. The adopted methodology enables efficient screening of significant factor effects in a large design space consisting of 35 factors (32-billion potential configurations) using merely 72 observations per benchmark application. We quantify and tabulate the significance of each of the 35 factors for 13 benchmark applications. While these tables provide various insights into Java performance, they consistently highlight the performance significance of the instruction delivery mechanism, especially the instruction cache and the ITLB design parameters. Furthermore, these tables enable the architect to identify processor bottlenecks for Java workloads by providing an estimate of the relative impact of various design decisions.

Input/Output (I/O) automata and the Temporal Logic of Actions (TLA) are two well-known techniques for the specification and verification of concurrent systems. Over the past few years, they have been extended to the so-called dynamic I/O automata and, respectively, Mobile TLA (MTLA) in order to be more appropriate for mobile agent systems. Dynamic I/O automata is just a mathematical model, whereas MTLA is a logic with a formally defined language. In this paper, therefore, we investigate how MTLA could be used as a formal language for the specification of dynamic I/O automata. We do this by writing an MTLA specification of a travel agent system which has been specified semi-formally in the literature on that model. In this specification, we deal with always existing agents as well as with an initially unknown number of dynamically created agents, with mobile and non-mobile agents, with I/O-automata-style communication, and with the changing communication capabilities of mobile agents. We have previously written a TLA specification of this system. This paper shows that an MTLA specification of such a system can be more elegant and faithful to the dynamic I/O automata definition because the agent existence and location can be expressed directly by using agent and location names instead of special variables as in TLA. It also shows how the reuse of names for dynamically created and destroyed agents within the dynamic I/O automata framework can be specified in MTLA.

Basic features of fretting and factors affecting its deleterious effects on the performance of electrical/electronic connection were reviewed. It was shown that although the fretting cannot be eliminated completely, its deleterious effects can be substantially reduced by lubrication and also connection design.

Negative bias temperature instability (NBTI) has become a critical reliability phenomena in advanced CMOS technology. In this paper, we propose an analytical temperature-aware dynamic NBTI model, which can be used in two circuit operation cases: executing tasks with different temperatures, and switching between active and standby mode. A PMOS Vth degradation model and a digital circuits' temporal performance degradation estimation method are developed based on our NBTI model. The simulation results show that: 1) the execution of a low temperature task can decrease ΔVth due to NBTI by 24.5%; 2) switching to standby mode can decrease ΔVth by 52.3%; 3) for ISCAS85 benchmark circuits, the delay degradation can decrease significantly if the circuit execute low temperature task or switch to standby mode; 4) we have also observed the execution time's ratio of different tasks and the ratio of active to standby time both have a considerable impact on NBTI effect.

In this study, I have numerically investigated the temperature distribution of n-type Si Nano Wire MOS Transistor induced by the self-heating effect by using a 3-D device simulator. The dependencies of temperature distribution within the Si Nano Wire MOS Transistor on both its gate length and width of the Si nano wire were analyzed. First, it is shown that the peak temperature in Si Nano Wire MOS Transistor increases by 100 K with scaling the gate length from 54 nm to 14 nm in the case of a 50 nm width Si nano wire. Next, it is found that the increase of its peak temperature due to scaling the gate length can be suppressed by scaling the size of the Si nano wire, for the first time. The peak temperature suppresses by 160 K with scaling the Si nano wire width from 50 nm to 10 nm in the case of a gate length of 14 nm. Furthermore, the heat dissipation in the gate, drain, and source direction are analyzed, and the analytical theory of the suppression of the temperature inside Si Nano Wire MOSFET is proposed. This study shows very useful results for future Si Nano Wire MOS Transistor design for suppressing the self-heating effect.

The binary exponential back-off mechanism is one of the basic elements that constitute the IEEE 802.11 protocol. The models of the back-off mechanism have been developed with the assumption that collisions occur only due to nodes within the carrier sensing range and the collision probability is constant in steady-state. However, the transmission collisions can occur due to hidden nodes and these tend to occur consecutively, contrary to the collisions due to nodes within the carrier sensing range. Consecutive collisions increase the back-off time exponentially, resulting in less frequent transmission attempts. Ignoring this collision characteristic in modeling the back-off mechanism can produce large errors in the performance analysis of networks. In this paper, we model the back-off process as a Markov renewal process by taking into account such consecutive collisions due to hidden nodes, and then compare this result with NS2 simulation results. According to the simulation results, the proposed model reduces the relative error in the attempt probability by more than 90% in the grid topology. We also propose a new collision model for a simple network considering consecutive collisions due to hidden nodes, and analyze the network under saturated traffic condition using the proposed models. The attempt and collision probabilities are estimated with high accuracy.

We propose a new band selective stop filter construction to decrease the out of band intermodulation distortion (IMD) noise generated in the transmitting power amplifier. Suppression of IMD noise directly improves the adjacent channel leakage power ratio (ACLR). A high-temperature superconducting (HTS) device with extremely high-Q performance with very small hybrid IC pattern would make it possible to implement the proposed filter construction as a practical device. To confirm the effectiveness of the HTS reaction-type filter (HTS-RTF) in improving ACLR, investigations based on both experiments and numerical analyses are carried out. The structure of a 5-GHz split open-ring resonator is investigated; its targets include high-unload Q-factor, low current densities, and low radiation. A designed 5-GHz HTS-RTF with 4 MHz suppression bandwidth and more than 40 dB MHz-1 sharp skirt is fabricated and experimentally investigated. The measured ACLR values are improved by a maximum of 12.8 dB and are constant up to the passband signal power of 40 dBm. In addition, to examine the power efficiency improvement offered by noise suppression of the HTS-RTF, numerical analyses based on measured results of gallium nitride HEMT power amplifier characteristics are conducted. The analyzed results shows the drain efficiency of the amplifier can be improved to 44.2% of the amplifier with the filter from the 15.7% of the without filter.