Since a logic circuit often has too many paths to test delay of all paths, it is necessary for path delay testing to limit the number of paths to be tested. The paths to be tested should have large delay because such paths more likely cause a fault. Additionally, a test set for the paths are required to detect other models of faults as many as possible. In this paper, we investigate two typical criteria of path selection for path delay testing. From our experiments, we observe that test patterns for the longest paths cannot cover many local delay defects such as transition faults.

A burnt pancake graph is a variant of Cayley graphs and its topology is suitable for massively parallel systems. However, for a burnt pancake graph, there is much room for further research. Hence, in this study, we focus on n-burnt pancake graphs and propose an algorithm to obtain n disjoint paths from a source node to n destination nodes in polynomial order time of n, n being the degree of the graph. In addition, we estimate the time complexity of the algorithm and the sum of path lengths. We also give a proof of correctness of the algorithm. Moreover, we report the results of computer simulation to evaluate the average performance of the algorithm.

Nowadays, the use of dependable systems is generalising, and diagnosis is an important step during their design . A diagnosis in early phases of the design cycle allows to save time and money. Fault injection can be used during the design process of the system, and using Hardware Description Languages, particularly VHDL, it is possible to accomplish this early diagnosis. During last years, the Time-Triggered Architecture (TTA) has emerged as a hard real-time fault-tolerant architecture for embedded systems. This novel architecture is gaining adepts mainly in the avionics and automotive industries ( x-by-wire ). The TTA implements a synchronous protocol with static scheduling that has been specifically targeted at hard real-time fault-tolerant distributed system. In this work, we present the study of the VHDL model of a communication controller based on the TTA, where a number of fault injection campaigns have been carried out. We comment the results produced and suggest some solutions to problems detected.

In this paper, we propose a fault-tolerance mechanism for microprocessors, which detects transient faults and recovers from them. The investigation of fault-tolerance techniques for microprocessors is driven by two issues: One regards deep submicron fabrication technologies. Future semiconductor technologies could become more susceptible to alpha particles and other cosmic radiation. The other is the increasing popularity of mobile platforms. Cellular telephones are currently used for applications which are critical to our financial security, such as mobile banking, mobile trading, and making airline ticket reservations. Such applications demand that computer systems work correctly. In light of this, we propose a mechanism which is based on an instruction reissue technique for incorrect data speculation recovery and utilizes time redundancy, and evaluate our proposal using a timing simulator.

The current congestion control mechanism for TCP with ECN suffers from the oscillation of the window size and the unfair sharing of network resources. These problems are caused by the insufficient information about the congestion level of a network and the different round trip time (RTT) among the connections respectively. In this paper, we propose a new window control algorithm for TCP with ECN to avoid the oscillation of the window size and to achieve the fairness among the connections.

Based on an experimental fact that surface wave plasmas excited by strongly coupled microwave through thin dielectric windows show nearly perfect absorption of microwave and, after diffusion, form a widely uniform dense plasma. A plasma with an uniformity of 5% over an area of 50 cm 60 cm was produced. The plasma produced by application of 2400 W total microwave power gives 1 1011 cm-3 in density and 1.5 eV in electron temperature.

This letter presents a simple A/D converter based on the circle map. The converter encodes a dc input into a binary output sequence and has the trapping window that extracts an available part of the output sequence. Using the available part, the decoder provides an estimation by a fraction with variable denominator: it can realize higher resolution. Theoretical evidences for the estimation characteristics are given.

For the channel estimation in the pilot channel aided CDMA systems which can support a multi-code scheme, we consider a linear prediction using both pilot and traffic channels. After deriving a new form of the optimal Wiener filter which requires less computational load, for its practical implementation, we propose the decision-directed adaptive linear prediction filter (DD-ALPF). To prevent from falling into the false lock, the proposed DD-ALPF uses the conventional channel estimate obtained only from pilot channel as a baseline for checking the reliability of the filter output. It will be shown through computer simulation that the proposed method can improve the receiver performance and performs better in the fast fading environments, compared with the existing ones.

This paper proposes a fast multi-cycle path detection method for large sequential circuits. The proposed method is based on ATPG techniques, especially on implication techniques, to use circuit structures and multi-cycle path conditions directly. The method also checks whether or not a multi-cycle path may be invalidated by static hazards at the inputs of flip-flops. Then we explain how to apply the proposed algorithm to real industrial designs. Experimental results show that our method is much faster than conventional ones and that it is efficient enough to handle large industrial designs.

By adding an auxiliary transformer to a single-stage single-switch power-factor-corrected converter (S4PFCC), the storage capacitor voltage and its range of voltage change against line voltage change are reduced. In addition, this transformer provides a direct power transfer path for input line to output load to increase the conversion efficiency. High power factor is maintained due to the elimination of dead angle of the input current. This paper presents detailed analysis and optimal design of a discontinuous conduction mode (DCM) boost-flyback S4PFCC with the auxiliary transformer. Experimental results for a 15 V/60 W prototype and with comparison to a S4PFCC without the auxiliary transformer are given to show the proposed approach effective.

In the paper we evaluate program susceptibility to hardware faults using fault injector. The performed experiments cover many applications with different features. The effectiveness of software techniques improving system dependability is analyzed. Practical aspects of embedding these techniques in real programs are discussed. They have significant impact on the final fault robustness.

We propose a new dependable system called PREGMA (Platform for Reliable Environment based on a General-purpose Machine Architecture). PREGMA aims to meet two requirements -- fault tolerance and low cost -- for Internet services. It can provide fault tolerance, so we can avoid system failure and prevent data corruption, even if faults occur. That is, it masks the faults by running multiple replicated servers, each possessing its own data, in a loosely synchronized manner and delivering the majority vote as output to clients. Moreover, PREGMA is composed of COTS (Commercial Off-The-Shelf) components without modification, which makes it possible to offer the services at a low cost. We investigated two approaches for achieving redundancy of the Coordinator, which is the core of PREGMA: using the primary backup method and the active replication method. We evaluated the effectiveness of PREGMA in terms of throughput overhead, data integrity and recovery time. The results for a prototype show that PREGMA using the Coordinator with the primary backup method outperforms that with the active replication method and has throughput only 3% lower than a non-redundant system. The results also show that, in the event of failure, the recovery time is only less than one second and no data corruption occurs.

A test generation method with time-expansion model can achieve high fault efficiency for acyclic sequential circuits, which can be obtained by partial scan design. This method, however, requires combinational test pattern generation algorithm that can deal with multiple stuck-at faults, even if the target faults are single stuck-at faults. In this paper, we propose a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults. Experimental results show that test sequences for acyclic sequential circuits with high fault efficiency are generated in small computational effort.

Since the characteristic to current information systems is the dynamic and concurrent change of their configurations and scales with non-stop provision of their services, the system management should inevitably rely on autonomic computing. Since fault tolerance is the one of important system management issues, it should also be incorporated in autonomic computing environment. This paper argues what should be taken into consideration and what approach could be available to realize the fault tolerance in such environments.

Iterative Logic Arrays (ILAs) are widely used in many applications, e.g., general-purpose processors, digital signal processors, and embedded processors. Owing to the advanced VLSI technology, new defect mechanisms exist in the fabricated circuits. In order to ascertain the quality of manufactured products, the traditional single cell fault model is not sufficient. Therefore, more realistic fault models such as sequential fault models and delay fault models should also be adopted. A cell delay fault occurs if and only if an input transition cannot be propagated to the cell's output through a path in the cell in a specified clock period. It has been shown that all SIC (single input change) pairs of a circuit are sufficient to detect all robustly detectable path delay faults within the circuit. We extend the concept of SIC pairs for iterative logic arrays. We say that an ILA is C-testable for cell delay faults if it is possible to apply all SIC pairs of a cell to each cell of the array in such a way that the number of test pairs for the array is a constant. This is based on a novel fault model, called Realistic Sequential Cell Fault Model (RS-CFM). Necessary conditions for sending this test set to each cell in the array and propagating faulty effects to the primary outputs are derived. An efficient algorithm is also presented to obtain such a test sequence. We use the pipelined array multiplier as an example to illustrate our approach. The number of test pairs for completely testing of the array is only 84. Moreover, the hardware overhead to make it delay fault testable is about 5.66%.

This paper presents the results of a continuing research work on the practical characterization of operating systems (OS) behavior in the presence of software faults in OS components, such as faulty device drivers. The methodology used is based on the emulation of software faults in device drivers and observation of the behavior of the overall system regarding a comprehensive set of failure modes, analyzed according to different dimensions related to multiple user perspectives. The emulation of the software faults is done through the injection of specific mutations at machine-code level that reproduce the code generated by compilers when typical programming errors occur in the high level language code. Two important aspects of this methodology are the independence of source code availability and the use of simple and established practices to evaluate operating systems failure modes, thus allowing its use as a dependability benchmarking technique. The generalization of the methodology to any software system built of discrete and identifiable components is also discussed.

This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the circuit-delay variation, so it is important to characterize each gate-delay variation accurately. Every transistor in a gate affects transient characteristics of the gate, so it is indispensable to consider an intra-gate variability for the modeling of gate-delay variation. This effect is not captured in a statistical delay analysis reported so far. Our model considers the intra-gate variability by sensitivity constants. We evaluate our modeling accuracy, and we show some simulated results of a circuit delay variation.

The application of fault injection in the context of dependability benchmarking is far from being straightforward. One decisive issue to be addressed is to what extent injected faults are representative of the considered faults. This paper proposes an approach to analyze the effects of real and injected faults.

26 GHz bandpass filter and duplexer using TM11δ rectangular-mode dielectric cavity resonators are proposed. These have a configuration compact and suitable for mounting on circuit boards. The resonators consisting of the Ba(Mg,Ta)O3 ceramic material showed a high quality factor value of 2600, which is roughly comparable to that of conventional E-plane waveguide filters. The dielectric losses of the ceramic material were experimentally evaluated from the viewpoint of the high frequency operation and the dielectric loss tangent of 7.410-5 was observed at 20 GHz. A three-stage Tchebyscheff bandpass filter with 0.4% relative bandwidth was fabricated and the passband insertion loss was 1.7 dB. A duplexer designed with two TM11δ mode filters and a microstrip T-junction is also presented.

Fault-tolerant execution of a mobile agent is an important design issue to build a reliable mobile agent system. Several fault-tolerant schemes for a single agent system have been proposed, however, there has been little research result on the multi-agent system. For the cooperating mobile agents, fault-tolerant schemes should consider the inter-agent dependency as well as the mobility; and try to localize the effect of a failure. In this paper, we investigate properties of inter-agent dependency and agent mobility; and then characterize rollback propagation caused by the dependency and the mobility. We then suggest some schemes to localize rollback propagation.