In this paper, a new method for displaying a surface deformation is proposed to provide sufficient realism in virtual environment. The approach selected in this paper is based on the fuzzy model and it is sufficient that only one additional rule be added to the fuzzy model to display a surface deformation. Furthermore, designers can easily determine which parameters should be used and how much they should be changed in order to alter shapes as required. The proposed method, thus, is a simple, but effective technique that can also be applied to real time operation and makes it possible to act on several surface points simultaneously. The results of the computer simulation are also given to demonstrate the validity of the proposed algorithm.

This paper first discusses the misinterpretation of the concept of "ubiquitous computing" that Mark Weiser originally proposed in 1991. Weiser's main message was not the ubiquity of computers, but the transparency of interface that determines users' perception of digital technologies embedded in our physical environment seamlessly. To explore Weiser's philosophy of transparency in interfaces, this paper presents the design of an interface that uses glass bottles as "containers" and "controls" for digital information. The metaphor is a perfume bottle: Instead of scent, the bottles have been filled with music -- classical, jazz, and techno music. Opening each bottle releases the sound of a specific instrument accompanied by dynamic colored light. Physical manipulation of the bottles -- opening and closing -- is the primary mode of interaction for controlling their musical contents. The bottles illustrates Mark Weiser's vision of the transparent (or invisible) interface that weaves itself into the fabric of everyday life. The bottles also exploits the emotional aspects of glass bottles that are tangible and visual, and evoke the smell of perfume and the taste of exotic beverages. This paper describes the design goals of the bottle interface, the arrangement of musical content, the implementation of the wireless electromagnetic tag technology, and the feedback from users who have played with the system.

This paper presents a network architecture with a dual interface IP handoff technique that allows smooth node mobility without using any intermediate proxy. The proposed architecture is suitable for low bit-rate time sensitive real time applications, where payload tends to be short and packet header overhead is particularly significant. Connections are established as per permanent addresses of the nodes but are carried on by the IP layer according to the temporary addresses by address translation within the end hosts. The mapping information is maintained by database servers, which can be placed in the Internet in a distributed manner. We describe the architecture and show its mobile capabilities by prototype implementation and performance evaluation. Furthermore a dual-interface handoff suitable to the proposed architecture is also introduced. Preliminary results show that the proposed architecture has significantly low overheads. It is compatible with the existing infrastructure and works fine in both IPv4 and IPv6 environments. Analysis also shows that with dual-interface handoff it is possible to achieve seamless handoff without any packet loss by exploiting overlapping coverage area and speed of the mobile node. Handoff latency is reduced significantly as compare to MIPv6. We believe that with more powerful network interface card drivers our concept of dual interface handoff can be realized.

There is a fatal difference in obtaining information between sighted people and the blind. Screen reading technology assists blind people in accessing digital documents by themselves helping to bridge such gap. However, these days they are becoming much more visual using various types of visual effects for sighted people to explore the information intuitively at a glance. It is very hard to convey visual effects non-visually and intuitively while retaining the original effects. In addition, it takes a long time to explore the information, since blind people use the keyboard for exploration, while sighted people use eye movement. This research aims at improving the non-visual exploration interface and improving the quality of non-visual information. Therefore, TAJODA (tactile jog dial interface) was proposed to solve these problems. It presents verbal information (text information) in the form of speech, while nonverbal information (visual effects) is represented in the form of tactile sensations. It uses a jog dial as an exploration device, which makes it possible to explore forward or backward intuitively in the speech information by spinning the jog dial clockwise or counterclockwise. It also integrates a tactile device to represent visual effects non-visually. Both speech and tactile information can be synchronized with the dial movements. The speed of spinning the dial affects the speech rate. The main part of this paper describes an experimental evaluation of the effectiveness of the proposed TAJODA interface. The experimental system used a preprocessed recorded human voice as test data. The training sessions showed that it was easy to learn how to use TAJODA. The comparison test session clearly showed that the subjects could perform the comparison task using TAJODA significantly faster (2.4 times faster) than with the comparison method that is closest to the existing screen reading function. Through this experiment, our results showed that TAJODA can drastically improve the non-visual exploration interface.

As we enter the deep submicron era, the costs to maintain the quality of shipped products increases significantly. Unfortunately, even 100% coverage of the widely used single stuck-at faults cannot guarantee that the defect level of the shipped chips is low enough. This is due to the fact that the stuck-at fault model does not cover all catastrophic defects. Moreover, it is difficult to estimate the difference between stuck-at fault coverage and defect coverage. Multiple fault models or test techniques are usually adopted in the test process, each having its corresponding fault coverage. However, the relationship between the defect level and those individual fault coverages remains to be explored. In this paper, we first propose the concept of multi-model fault coverage (MFC) instead of the fault coverage based on a single fault model. The multi-model fault coverage for nonequiprobable faults is presented, and the multi-model fault coverage for equiprobable faults is shown to be a special case of nonequiprobable faults. The relationship between defect level, fabrication yield, and multi-model fault coverage is then derived. We also analyze the defect level error between the predicted defect level and the physical defect level. An algorithm is also proposed for estimating the number of fault models required in order to achieve sufficient accuracy. Experimental results show that multi-model fault coverage can be used to predict the defect level more precisely. As the number of fault models increases, the defect level error reduces significantly. Our approach is efficient for product quality prediction, especially for deep sub-micron devices.

This paper proposes a novel method of identifying the design parameters for a practical implementation of the fair queueing discipline, which is capable of class-level delay control. The notion of class weight is introduced at first, and then the session weights are determined. This two-phase approach is favorable in terms of the scalability;that is, the overall complexity is dependent upon the number of classes only. We propose a packet scheduler referred to as the DPS (Delay-centric Processor Sharing) scheme which employs those design parameters to deliver class-wise delay bound services. The associated admission policy for delay guarantee is also derived. System analysis and derivation of the parameters have their origins in the understanding of the so-called system equation, which describes the dynamics of the class-level service share. The proposed design parameters are QoS-aware in that they are consistently refined depending on the system status. Several numerical and simulation results show that the DPS scheme is advantageous over other ones in terms of both resource efficiency and the robustness. Concerning the scalability, we show that an alternative tagging process of the DPS scheme is implementable with O(1) complexity with no significant degradation in delay performance.

We had previously proposed a fuzzy logic-based buffer management scheme (BMS) called fuzzy early detection (FED), which was designed to improve transmission control protocol (TCP) performance over the unspecified bit rate (UBR) service of asynchronous transfer mode (ATM) networks. Since a weakness in FED was discovered later, we present a refined version of it named FED+ here. Maintaining the design architecture and the algorithm of FED, FED+ further adopts a specific per virtual connection accounting algorithm to achieve its design goals. The effects of TCP implementation, TCP maximum segment size, switch buffer size and network propagation delay on FED+ performance are studied through simulation. Its performance is then compared with those of pure early packet discard (EPD), P-random early detection (P-RED) and FED. Our evaluations show that FED+ is superior to the others if the issues of efficiency, fairness, robustness, buffer requirement and the ease of tuning control parameters of a BMS are considered collectively.

Precise designs are presented for sapphire rod resonators of three types, which have been proposed by the IEC/TC90/WG8 in the standard measurement method of the surface resistance Rs of high-Tc superconductor (HTS) films; an open-type, a cavity-type and a closed-type. In order to separate TE011 and TE013 modes, which are used in Rs measurements, from the other modes, appropriate dimensions for these three resonators are determined from mode charts calculated from a rigorous analysis based on the mode matching method, taking account of an uniaxial-anisotropic characteristic of sapphire. Comparison of the open-type resonator with the closed-type is performed. For the open-type, the unloaded Q values of both the TE011 and TE013 modes are reduced by radiations of a leaky state TM310 mode. Finally, validity of the design and a two-sapphire-rod-resonator method will be verified by experiments.

A CMOS DFE (decision feedback equalization) receiver with a clock-data skew compensation was implemented for the SSTL (stub-series terminated logic) SDRAM interface. The receiver consists of a 2 way interleaving DFE input buffer for ISI reduction and a X2 over-sampling phase detector for finding the optimum sampling clock position. The measurement results at 1.2 Gbps operation showed the increase of voltage margin by about 20% and the decrease of time jitter in the recovered sampling clock by about 40% by equalization in an SSTL channel with 2 pF 4 stub load. Active chip area and power consumption are 3001000 µm2 and 142 mW, respectively, with a 2.5 V, 0.25 µm CMOS process.

In this paper, we derive expressions for the bit error probability of QPSK/OFDM on frequency-selective Rayleigh fading channels. In the OFDM system, ICI (interchannel interference) caused by Doppler spread of the channel degrades the error performance of the system and introduces the error floor even for coherent detection. Analysis results show that the error performance of QPSK/OFDM can be degraded as the normalized maximum Doppler frequency fD /Bsub is increased where fD is the maximum Doppler frequency and Bsub is the subchannel bandwidth. Computer simulations confirm the theoretical analysis results for BPSK and QPSK signals.

In mobile multimedia environment, it is very important to minimize handoff latency due to mobility. In terms of reducing handoff latency, Hierarchical Mobile IPv6 (HMIPv6) can be an efficient approach, which uses a mobility agent called Mobility Anchor Point (MAP) in order to localize registration process. However, MAP can be a single point of failure or performance bottleneck. In order to provide mobile users with satisfactory quality of service and fault-tolerant service, it is required to cope with the failure of mobility agents. In, we proposed Robust Hierarchical Mobile IPv6 (RH-MIPv6), which is an enhanced HMIPv6 for fault-tolerant mobile services. In RH-MIPv6, an MN configures two regional CoA and registers them to two MAPs during binding update procedures. When a MAP fails, MNs serviced by the faulty MAP (i.e., primary MAP) can be served by a failure-free MAP (i.e., secondary MAP) by failure detection/recovery schemes in the case of the RH-MIPv6. In this paper, we investigate the comparative study of RH-MIPv6 and HMIPv6 under several performance factors such as MAP unavailability, MAP reliability, packet loss rate, and MAP blocking probability. To do this, we utilize a semi-Markov chain and a M/G/C/C queuing model. Numerical results indicate that RH-MIPv6 outperforms HMIPv6 for all performance factors, especially when failure rate is high.

To examine the computational complexity of cryptographic primitives such as the discrete logarithm problem, the factoring problem and the Diffie-Hellman problem, we define a new problem called square-root exponent, which is a problem to compute a value whose discrete logarithm is a square root of the discrete logarithm of a given value. We analyze reduction between the discrete logarithm problem modulo a prime and the factoring problem through the square-root exponent. We also examine reductions among the computational version and the decisional version of the square-root exponent and the Diffie-Hellman problem and show that the gap between the computational square-root exponent and the decisional square-root exponent partially overlaps with the gap between the computational Diffie-Hellman and the decisional Diffie-Hellman under some condition.

General closed-form expressions are derived and analyzed for the exact bit error rate (BER) performance of the arbitrary rectangular Gray coded QAM signal in conjunction with maximal-ratio combining (MRC) diversity on frequency non-selective slow m-distributed Nakagami fading channel. The analyses consider four channel models, independent and identical, independent and nonidentical, identical but correlated, and arbitrary correlated fading. Numerical results demonstrate error performance improvement with the use of MRC diversity reception. The new expressions presented here are suitable for evaluating various cases of practical interest on wireless communication channels.

The notion of k-wise independent permutations has several applications. From the practical point of view, it often suffices to consider almost (i.e., ε-approximate) k-wise independent permutation families rather than k-wise independent permutation families, however, we know little about how to construct families of ε-approximate k-wise independent permutations of small size. For any n > 0, let Sn be the set of all permutations on {0,1,..., n - 1}. In this paper, we investigate the size of families of ε-approximate k-wise independent permutations and show that (1) for any constant ε 0, if a family Sn of permutations is ε-approximate k-wise independent, then || n(n - 1) (n - k + 1) if ε< 1; || {n(n - 1) (n - k + 1)}/(1 +ε) otherwise; (2) for any constant 0< ε 1, there exists a family Sn of ε-approximate k-wise independent permutations such that || = ; (3) for any constant ε> 0 and any n = pm - 1 with p prime, it is possible to construct a polynomial time samplable family Sn of ε-approximate pairwise independent permutations such that || = O(n(n - 1)/ε); (4) for any constant ε> 0 and any n = pm with p prime, it is possible to construct a polynomial time samplable family Sn of ε-approximate 3-wise independent permutations such that || = O(n(n - 1)(n - 2)/ε). Our results are derived by combinatorial arguments, i.e., probabilistic methods and linear algebra methods.

This paper considers a wireless LAN system operated in a multiple-cell environment with universal frequency reuse. A key technical goal is to increase cell-capacity within a cell. A very high-rate wireless LAN system, maximum data rates of over 100 Mbit/s, is proposed that offers an expanded signal-bandwidth compared to that specified in IEEE802.11a. The system employs OFDM and MC/CDMA signals in packet mode. It falls back from OFDM signals with low subcarrier modulation orders to MC/CDMA signals. A link level performance comparison shows that OFDM has superior performance to MC/CDMA at over 32 Mbit/s. Under 16 Mbit/s, however, MC/CDMA can establish wireless link connections unlike OFDM. Thus the fallback technique, which is triggered by the CIR environment, should select OFDM if the data rate exceeds 32 Mbit/s. It should fallback to MC/CDMA if the rate is less than 16 Mbit/s. We also evaluate the proposed scheme in a multiple-cell environment with universal frequency reuse, where the severe co-channel (other-cell) interference is present. We derive a cell capacity criterion for wireless LAN systems, and show that the proposed scheme offers a 2.2 times larger available transmission distance than the OFDM-only scheme. In addition, it is found that the proposed scheme offers a 1.3 times improvement in cell capacity compared to the MC/CDMA-only scheme, even if all other-cell interference is considered.

This paper proposes a framework for distributed network management by incorporating fault and performance management metrics in a hierarchical decision making model. The goal of this research is to automate the fault management process. The fault management system is organized as a three level information processing model. Correlation results from each level are provided as evidence to the next level. Causal and temporal relationships between monitored variables are captured using Dynamic Bayesian Networks. As evidence is gathered, the probability of the presence of a fault is either strengthened or weakened. The proposed model is used for proactive fault detection as well as fault isolation purposes. A prototype implementing the ideas is presented.

Refactoring is one of the promising techniques for improving software design by means of behavior-preserving structural transformation, and is widely taken into practice. In particular, it is frequently applied to design models represented with UML such as class diagrams. However, since UML design models includes multiple diagrams which are closely related from various views, to get behavior-preserving property, we should get the other types of design information and should handle with the propagation of the change on a diagram to the other diagrams. For example, to refactor a class diagram, we need behavioral information of methods included in the class and should also refactor diagrams which represent the behavior, such as state diagrams, activity diagrams. In this paper, we introduce refactoring on design models as transformations of a graph described by UML class diagram and action semantics. First, we define basic transformations of design models that preserve the behavior of designed software, and compose them into refactoring operations. We use Object Constraint Language (OCL) to specify when we can apply a refactoring operation. Furthermore we implement our technique on a graph transformation system AGG to support the automation of refactoring, together with evaluation mechanism of OCL expressions. Some illustrations are presented to show its effectiveness. The work is the first step to handle with refactoring on UML design models in integrated way.

A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource-saving multi-datapath radix-23 computation element. The 2-stage CMA, including a pair of single-port SRAMs, is also introduced to speedup the execution time of the 2-dimensional FFTs. Using the above techniques, we have designed an FFT processor core which integrates 552,000 transistors within an area of 2.82.8 mm2 with CMOS 0.35 µm triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, 1-dimensonal FFT in 23.2 µsec and a 2-dimensional one in only 23.8 msec at 133 MHz operation. The power consumption of this processor is 439.6 mW at 3.3 V, 100 MHz operation.

Comparison of intelligent and random testing in data inputting is still under discussion. Little is also known about testing for the whole software and empirical testing methodology when random testing used. This study research not only for data inputting testing, but also operation of software (called transitions) in order to test the whole GUI software by intelligent and random testing. Methodology of this study is that we attempt to research efficiency of random and intelligent testing by Chinese postman problem. In general, random testing is considered straightforward but not efficient. Chinese postman problem testing is complicated but efficient. The comparison between random and intelligent testing would give further recommendation for software testing methodology.

In this paper, we study DS-CDMA delay transmit diversity that transmits the weighted and time-delayed versions of the same signal from multiple antennas in a frequency non-selective fading environment. At a receiver, one receive antenna is used and the received delayed signals are coherently combined by Rake receiver. The set of optimum antenna weights for maximizing the received signal-to-noise power ratio (SNR) is theoretically derived to reveal that the optimum solution is to transmit only from the best antenna that has the maximum channel gain. The bit error rate (BER) performance improvement over conventional delay transmit diversity is theoretically analyzed and confirmed by computer simulations. The combined effect of transmit diversity and transmit power control (TPC) is also evaluated. Furthermore, the impact of fading decorrelation between the transmit and receive channels is also investigated for both the time division duplex (TDD) and frequency division duplex (FDD) schemes.