Akihisa CHIKAMURA Koji NAKAMAE Hiromu FUJIOKA
The effect of lot size change and test processing logistics on VLSI manufacturing final test process efficiency and cost due to the transition of from conventional 5 or 6 inches to 300 mm (12 inches) in wafer size is evaluated through simulation analysis. Simulated results show that a high test efficiency and a low test cost are maintained regardless of arrival lot size in the range of the number of 300 mm wafers per lot from 1 to 25 and the content of express lots in the range of up to 50% by using WEIGHT+RPM rule and the right final test processing logistics. WEIGHT+RPM rule is the rule that considers the jig and temperature exchanging time, the lot waiting time in queue and also the remaining processing time of the machine in use. The logistics has a small processing and moving lot size equal to the batch size of testing equipment.
Kazuhito MURAKAMI Nobuo OKAMOTO Yasumasa NOGUCHI
A simple simulation approach based on the modified central difference (MCD) method for analyzing the coupling characteristics of coupled transmission lines (CTL) is presented. Gaussian pulse responses on the sense line are demonstrated by graphical expressions. The frequency characteristics of the coupling factor is efficiently derived from the extracted input and output responses by using the fast Fourier transform (FFT) technique. It is shown that this approach is useful to analyze the coupling characteristics of symmetrical and asymmetric multi-section CTL.
Katsuhisa MARUYAMA Shozo NAITO
As network services become more diverse and powerful, service applications that perform such services are acquiring an ever-larger amount of complicated and changeable relationships. We present a network dependence graph (NDG) that captures both data and control flow relationships between components of service applications that work collaboratively. This graph is constructed based on analysis of both the behavior of each of the service applications and their configuration, which describes the device names they refer to, and allows network slicing to be implemented as a simple graph traversal. Network slicing is the extraction of necessary and minimum service components that may affect the execution of a specified service application; it helps a network manager to find the location of service faults lurking somewhere in the network. We also present a method for locating faults that uses network slicing and a system based on this method.
Hitoshi OKAMURA Masaharu SATO Satoshi NAKAMURA Shuji KISHI Kunio KOKUBU
This paper describes a newly developed FET Coupled Logic (FCL) circuit that operates at very high frequencies with very low supply voltages below 3.3 V. An FCL circuit consists of NMOS source-coupled transistor pairs for current switches, load resistors, emitter followers and current sources that are controlled by a band-gap reference bias generator. The characteristics and performance are discussed by comparing this circuit with other high-speed circuits. The optimal circuit parameters for FCL circuits are also discussed, and the fact is noted that a larger swing voltage enhances the circuit's performance. The simulated delay of a 0.25 µm FCL circuit is less than 15 ps for a 2.5 V power supply, and the simulated maximum toggle frequencies are over 5 GHz and 10 GHz at 2.5 V and 3.3 V power supply, respectively. The simulation results show that FCL circuits achieve the best performance among the current mode circuits, which include ECL circuits, NMOS source-coupled logic circuits. The delay of the FCL circuit is less than half that of an ECL circuit. The maximum toggle frequency of the FCL circuit is about triple that of NMOS source-coupled logic circuit. Because the FCL circuit uses low-cost CMOS-based BiCMOS technologies, its cost performance is superior to ECL circuits that require expensive base-emitter self-aligned processes and trench isolation processes. Using depletion-mode NMOS transistors for current switches can lower the minimum supply voltage for FCL circuits and it is below 1.5 V. The FCL circuit is a promising logic gate circuit for multi-Gbit/s tele/data communication LSIs.
Shih-Chang WANG Jeng-Ping LIN Sy-Yen KUO
In this paper, we propose a novel fault-tolerant multicast algorithm for n-dimensional wormhole routed hypercubes. The multicast algorithm will remain functional if the number of faulty nodes in an n-dimensional hypercube is less than n. Multicast is the delivery of the same message from one source node to an arbitrary number of destination nodes. Recently, wormhole routing has become one of the most popular switching techniques in new generation multicomputers. Previous researches have focused on fault-tolerant one-to-one routing algorithms for n-dimensional meshes. However, little research has been done on fault-tolerant one-to-many (multicast) routing algorithms due to the difficulty in achieving deadlock-free routing on faulty networks. We will develop such an algorithm for faulty hypercubes. Our approach is not based on adding physical or virtual channels to the network topology. Instead, we integrate several techniques such as partitioning of nodes, partitioning of channels, node label assignments, and dual-path multicast to achieve fault tolerance. Both theoretical analysis and simulation are performed to demonstrate the effectiveness of the proposed algorithm.
Jong Youl LEE Young Mo CHUNG Sang Uk LEE
In this paper, the bit error rate (BER) of 16 differential amplitude phase shift keying (16DAPSK) modems in future mobile communication system is derived analytically. The channel employed in this paper is the frequency-selective and fast Rayleigh fading channel, corrupted by cochannel interference (CCI) and additive white Gaussian noise (AWGN). Exact expressions for the probability distributions of the differential phase and amplitude ratio are derived for the BER calculation. The BER and optimum boundary are obtained for various channel conditions. In addition, the results for the BER in the presence of CCI are provided.
Yasuhiro KONISHI Yasunobu NAKASE Katsushi ASAHINA Makoto TANIGUCHI Michihiro YAMADA
Various I/O interface technologies in today's PC platform are classified into four categories, (1) ASIC (memory Controller) from / to Main Memory, (2) MPU from /to ASIC (Memory Controller), (3) ASIC (Memory Controller) from / to ASIC (Graphic Controller) and (4) ASIC from / to Peripherals. As to Category 1, effectiveness of SSTL is shown in DIMM application of SDRAM and DDR SDRAM over 100 MHz frequency. Furthermore a comparison is made between SLDRAM and D- RDRAM from the technology point of view. Concerning Categories 2 through 4, several interfaces such as PCI, AGP, GTL, HSTL and LVDS are reviewed. Interface technologies will keep playing an important role since computer systems require higher and higher speeds.
The author proposes a flow control scheme which derives the optimal packet transmission rate from the ACKs of the sending packets. The optimization is based on mathematical programming such as the extremal method and least-squares method. The author proves that the proposed method is fair when the RTT and thepacket length of each sender are the same. It is also shown that the sufficient condition for the proposed method to be optimal and stable generally holds true in packet networks. The performances are examined by computer simulations, and it is found that high throughput is obtained regardless of the network structure.
Shigeki OBOTE Yasuaki SUMI Naoki KITAI Kouichi SYOUBU Yutaka FUKUI Yoshio ITOH
In this paper, we propose a speedup method of frequency switching time in the phase locked loop (PLL) frequency synthesizer using the target frequency detector (TFD). The TFD detects the time Ta for any channels where the output of the PLL frequency synthesizer reaches the target frequency for the first time. At Ta, the programmable divider, the reference divider and the phase comparator are reset, and the phase of the PLL frequency synthesizer is initialized and the phase synchronization is achieved. In the proposed method, since the ringing in the transient state does not occur, the output of the PLL frequency synthesizer converges to the target frequency at Ta and the frequency switching time is speeded up. The effectiveness of the proposed method will be confirmed by experimental results.
Hideyuki IMAI Akira TANAKA Masaaki MIYAKOSHI
Optimum filters for an image restoration are formed by a degradation operator, a covariance operator of original images, and one of noise. However, in a practical image restoration problem, the degradation operator and the covariance operators are estimated on the basis of empirical knowledge. Thus, it appears that they differ from the true ones. When we restore a degraded image by an optimum filter belonging to the family of Projection Filters and Parametric Projection Filters, it is shown that small deviations in the degradation operator and the covariance matrix can cause a large deviation in a restored image. In this paper, we propose new optimum filters based on the regularization method called the family of Regularized Projection Filters, and show that they are stable to deviations in operators. Moreover, some numerical examples follow to confirm that our description is valid.
Masahide KANEKO Osamu HASEGAWA
Human faces convey various information, including that is specific to each individual person and that is part of mutual communication among persons. Information exhibited by a "face" is what is called "non-verbal information" and usually verbal media cannot easily describe such information appropriately. Recently, detailed studies on the processing of face images by a computer have been carried out in the engineering field for applications to communication media and human computer interaction as well as automatic identification of human faces. Two main technical topics are the recognition of human faces and the synthesis of face images. The objective of the former is to enable a computer to detect and identify users and further to recognize their facial expressions, while that of the latter is to provide a natural and impressive user interface on a computer in the form of a "face. " These studies have also been found to be useful in various non-engineering fields related to a face, such as psychology, anthropology, cosmetology and dentistry. Most of the studies in these different fields have been carried out independently up to now, although all of them deal with a "face. " Now in virtue of the progress in the above engineering technologies a common study tools and databases for facial information have become available. On the basis of these backgrounds, this paper surveys recent research trends in the processing of face images by a computer and its typical applications. Firstly, the various characteristics of faces are considered. Secondly, recent research activities in the recognition and synthesis of face images are outlined. Thirdly, the applications of digital processing methods of facial information are discussed from several standpoints: intelligent image coding, media handling, human computer interaction, caricature, facial impression, psychological and medical applications. The common tools and databases used in the studies of processing of facial information and some related topics are also described.
Ryusuke KAWANO Naoaki YAMANAKA Eiji OKI Tomoaki KAWAMURA
A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To raise the limit on the number of I/O pins, this circuit operates with a reference signal directly generated from the input signal itself. The reference level is changed dynamically to achieve a larger noise margin for operation. Experimental results show that operation up to 3.4 Gbps with a large level margin can be attained. We deploy this circuit to the input interface LSIs of an 80-Gbps ATM switching MCM.
The reconstruction of motion and structure from multiple images is fundamental and important problem in computer vision. This paper highlights the recovery of the camera motion and the object shape under some camera projection model from feature correspondences especially the epipolar geometry and the factorization method for mainly used projection models.
Jun-ichiro TORIWAKI Kensaku MORI
In this article we present a survey of medical image processing with the stress on applications of image generation and pattern recognition / understanding to computer aided diagnosis (CAD) and surgery (CAS). First, topics and fields of research in medical image processing are summarized. Second the importance of the 3D image processing and the use of virtualized human body (VHB) is pointed out. Thirdly the visualization and the observation methods of the VHB are introduced. In the forth section the virtualized endoscope system is presented from the viewpoint of the observation of the VHB with the moving viewpoints. The fifth topic is the use of VHB with deformation such as the simulation of surgical operation, intra-operative aids and image overlay. In the seventh section several topics on image processing methodologies are introduced including model generation, registration, segmentation, rendering and the use of knowledge processing.
Shigeru NAKAMURA Yoshiyasu UENO Kazuhito TAJIMA
We experimentally demonstrate the ultrafast and high-repetition capabilities of a polarization-discriminating symmetric Mach-Zehnder (PD-SMZ) all-optical switch. This switch, as well as an original symmetric Mach-Zehnder (SMZ) all-optical switch, is based on a highly efficient but slowly relaxing band-filling effect that is resonantly excited in a passive InGaAsP bulk waveguide. By using a mechanism that cancels out the effect of the slow relaxation, ultrafast switching is attained. We achieve a switching time of 200 fs and demultiplexing of 1.5 Tbps, showing the applicability of the SMZ or PD-SMZ all-optical switches to optical demultiplexing of well over 1 Tbps for the first time. High-repetition capability, which is another important issue apart from the switching speed, is also verified by using control pulses at a repetition rate of 10.5 GHz. We also discuss the use of nonlinearity in a semiconductor optical amplifier to further reduce the control-pulse energy.
Takemasa TAMANUKI Shotaro KITAMURA Hiroshi HATAKEYAMA Tatsuya SASAKI Masayuki YAMAGUCHI
Spot-size-converter integrated semiconductor optical amplifiers have been developed as gate elements for optical switch matrices. An S-shape waveguide has been introduced to prevent re-coupling of unguided light to the output fiber. An angled-facet structure effectively suppressed light reflection at the end facets. Consequently, a high extinction ratio of 70 dB and a high fiber-to-fiber gain of 20 dB were achieved. Sufficient optical coupling characteristics to a flat-ended single-mode fiber with a coupling loss of 3.5 dB were also demonstrated.
Shinji MINO Tohru MATSUNAGA Yasuo SHIBATA Akira MISAWA Yoshiaki YAMADA Keishi HABARA
A photonic ATM switch based on wavelength-division multiplexing will include several lossy passive devices, erbium-doped fiber amplifiers, and semiconductor optical amplifiers (SOAs) in a cascade configuration for fast switching of ns order. Its level diagram, which is very different from those of optical transmission links, has not been adequately studied. This paper investigates the concept of basing the level design of the photonic asynchronous-transfer-mode (ATM) switch we are developing on its Q-factor. First, we derive formulation of the Q-factor in a single PD and a dual-PD in a Manchester-encoded signal, which has several merits in packet switching and that we believe will become popular in photonic packet switches. Using this formula, we show an example of the level-diagram design including the Q factor calculation in an optical combiner and distributor section without SOA in our photonic ATM switch. Next, we showed experimentally that the pattern effect in SOAs can be suppressed by using a Manchester-encoded signal. Finally, we confirm that the allowable minimum level diagram in the switch can be based on a simple Q calculation and easy measurement of a bit error rate (BER) in a back-to-back configuration when using a Manchester-encoded signal. These results show that basing the level design of photonic ATM switches on the Q factor is feasible when using a Manchester signals. This approach can be applied to various types of photonic packet switches.
Shinji MINO Tohru MATSUNAGA Yasuo SHIBATA Akira MISAWA Yoshiaki YAMADA Keishi HABARA
A photonic ATM switch based on wavelength-division multiplexing will include several lossy passive devices, erbium-doped fiber amplifiers, and semiconductor optical amplifiers (SOAs) in a cascade configuration for fast switching of ns order. Its level diagram, which is very different from those of optical transmission links, has not been adequately studied. This paper investigates the concept of basing the level design of the photonic asynchronous-transfer-mode (ATM) switch we are developing on its Q-factor. First, we derive formulation of the Q-factor in a single PD and a dual-PD in a Manchester-encoded signal, which has several merits in packet switching and that we believe will become popular in photonic packet switches. Using this formula, we show an example of the level-diagram design including the Q factor calculation in an optical combiner and distributor section without SOA in our photonic ATM switch. Next, we showed experimentally that the pattern effect in SOAs can be suppressed by using a Manchester-encoded signal. Finally, we confirm that the allowable minimum level diagram in the switch can be based on a simple Q calculation and easy measurement of a bit error rate (BER) in a back-to-back configuration when using a Manchester-encoded signal. These results show that basing the level design of photonic ATM switches on the Q factor is feasible when using a Manchester signals. This approach can be applied to various types of photonic packet switches.
Takemasa TAMANUKI Shotaro KITAMURA Hiroshi HATAKEYAMA Tatsuya SASAKI Masayuki YAMAGUCHI
Spot-size-converter integrated semiconductor optical amplifiers have been developed as gate elements for optical switch matrices. An S-shape waveguide has been introduced to prevent re-coupling of unguided light to the output fiber. An angled-facet structure effectively suppressed light reflection at the end facets. Consequently, a high extinction ratio of 70 dB and a high fiber-to-fiber gain of 20 dB were achieved. Sufficient optical coupling characteristics to a flat-ended single-mode fiber with a coupling loss of 3.5 dB were also demonstrated.
Shigeru NAKAMURA Yoshiyasu UENO Kazuhito TAJIMA
We experimentally demonstrate the ultrafast and high-repetition capabilities of a polarization-discriminating symmetric Mach-Zehnder (PD-SMZ) all-optical switch. This switch, as well as an original symmetric Mach-Zehnder (SMZ) all-optical switch, is based on a highly efficient but slowly relaxing band-filling effect that is resonantly excited in a passive InGaAsP bulk waveguide. By using a mechanism that cancels out the effect of the slow relaxation, ultrafast switching is attained. We achieve a switching time of 200 fs and demultiplexing of 1.5 Tbps, showing the applicability of the SMZ or PD-SMZ all-optical switches to optical demultiplexing of well over 1 Tbps for the first time. High-repetition capability, which is another important issue apart from the switching speed, is also verified by using control pulses at a repetition rate of 10.5 GHz. We also discuss the use of nonlinearity in a semiconductor optical amplifier to further reduce the control-pulse energy.