The Finite-Difference Time-Domain (FDTD) method has been applied to study the scattering characteristics of Fabry-Perot cavities with infinite planar periodic surfaces. Periodic Boundary Conditions (PBC) are used to reduce the analysis to one unit periodic volume. Both dielectric and metallic losses are included in the algorithm using a frequency dependent formalism. This technique is used to study the frequency response of plane parallel Fabry-Perot cavities with square aperture metal mesh mirrors. These cavities are assumed to be illuminated by a normally incident plane wave. After a detailed description of the algorithm, we show theoretically the separate effects of dielectric and metal losses on the transmission coefficient of such cavities. We compare also simulation results to measurements, in the 60 GHz band, of resonant frequencies and Q factors of cavities with various mesh parameters.

This paper proposes an adaptive transmission control scheme for code-division multiple-access (CDMA) cellular slotted-ALOHA systems. This scheme adaptively controls the target received power and the processing gain according to both channel load and location of the mobile station. The target received power of each mobile station is controlled so that the difference between the target received powers by distance becomes large under heavy load conditions. As the distance from the base station increases, the target received power becomes smaller. The processing gain of transmitted packets is concurrently controlled with their target received powers. The packets transmitted with low signal power are spread by a large processing gain in order to reduce the unfairness in packet reception. The radio channels with distance attenuation, shadowing, slow Rayleigh fading and imperfect power control are taken into consideration in order to evaluate the performance of this scheme in the case that mobile stations transmit short massages to the base station in cellular environments. Computer simulation validates the effectiveness of this scheme: the capture effect can be achieved under heavy channel loads, and therefore, throughput performance is improved. Detailed evaluation of throughput, packet reception probability and transmission complete probability is presented. The effect of movement of mobile stations is also discussed. Calculated results show that the proposed scheme has superior characteristics and thus can expand the allowable load area in the cellular environments with slow Rayleigh fading channels.

Problems of flipped-chip MMIC at millimeter-wave frequency are investigated. Practical design criteria are introduced to obtain resonance and cutoff frequency for parasitic mode with flipped-chip MMIC structure. We investigate the advantages and disadvantages of three types of transmission line for flipped-chip MMIC in both electromagnetic simulation and scale-model. To avoid the resonance in coplanar waveguide flipped-chip MMIC new bridge structure is proposed.

CTL (Computation Tree Logic) model checking is a formal method for design verification that checks whether the behavior of the verified system is contained in that of the requirements specification. If this check doesn't pass, the CTL model checker generates a subset of fair states which belongs to the system but not to the specification. In this letter, we present an incremental method which successively modifies the latest verification result each time the design is modified. Our incremental algorithm allows the designer to make changes in terms of addition or subtraction of fair CTL formulas, or fairness constraints on acceptable behavior from the problem statement. Then, these changes are adopted to update the set of fair states computed earlier. Our incremental algorithm is shown to be better than the current non-incremental techniques for CTL model checking. Furthermore, a conclusion supported by the experimental results is presented herein.

Our simulation method by using a combination of discrete event simulation and detailed parametric models of the VLSI manufacturing test system is verified by comparing simulated results with actual ones of a real wafer test facility of one-chip microcomputer in a Japanese semiconductor company. The simulated results are found to be in close agreement with the actual ones. As an application of the verified simulation method, we evaluate the economic effect of the introduction in the wafer test process of LSI testers that allows us to test multiple chips simultaneously. It is found that the optimum number of chips simultaneously tested by an LSI tester is 4 when considering both of the test cost per chip and the average test TAT.

TCAD (Technology Computer Aided Design) is the simulation of semiconductor processes and devices. Despite twenty years of development, there are still many TCAD skeptics. This paper will discuss some of the problems and limitations of TCAD, present some successful examples of its use, and discuss future simulation needs from a user's perspective. A key point is that the time pressures in modern semiconductor technology development often dictate the use of simple models for approximate results.

We have developed a practical 3-D integrated process simulator (3-D MIPS) based on the orthogonal grid. 3-D MIPS has a 3-D topography simulator (3-D MULSS) and 3-D impurity simulator which simulates the processes of ion implantation, impurity diffusion and oxidation. In particular, its diffusion and segregation model is new and practical. It assumes the continuity of impurity concentration at the material boundary in order to coordinate with the topography simulator (3-D MULSS) with cells in which two or more kinds of materials exist. And then, we introduced a time-step control method using the Dufort-Frankel method of diffusion analysis for stable calculation, and a selective oxidation model to apply to more general structures than LOCOS structure. After that, the 3-D MIPS diffusion model is evaluated compared with experimental data. Finally, the 3-D MIPS is applied to 3-D simulations of the nMOS Tr. structure with LOCOS isolation, wiring interconnect and pn-junction capacitances, and DRAM storage node area.

In this paper, we propose methods for testing the usability of graphical user interface (GUI) applications based on log files of user interactions. Log analysis by existing methods is not efficient because evaluators analyze a single log file or log files of the same user and then manually compare results. The methods proposed here solve this problem; the methods enable evaluators to analyze the log files of multiple users together by detecting interaction patterns that commonly appear in the log files. To achieve the methods, we first clarify usability attributes that can be evaluated by a log-based usability testing method and user interaction patterns that have to be detected for the evaluation. Based on an investigation on the information that can be obtained from the log files, we extract the attributes of clarity, safety, simplicity, and continuity. For the evaluations of clarity and safety, the interaction patterns that have to be detected include those from user errors. We then propose our methods for detecting interaction patterns from the log files of multiple users. Patterns that commonly appear in the log files are detected by utilizing a repeating pattern detection algorithm. By regarding an operation sequence recorded in a log file as a string and concatenating strings, common patterns are able to be detected as repeating patterns in the concatenated string. We next describe the implementation of the methods in a computer tool for log-based usability testing. The tool, GUITESTER, records user-application interactions into log files, generates usability analysis data from the log files by applying the proposed methods, and visualizes the generated usability analysis data. To show the effectiveness of GUITESTER in finding usability problems, we report an example of a usability test. In this test, evaluators could find 14 problems in a tested GUI application. We finally discuss the ability of the proposed methods in terms of its log analysis efficiency, by comparing the analysis/sequence time (AT/ST) ratio of GUITESTER with those of other methods and tools. The ratio of GUITESTER is found to be smaller. This indicates the methods make log analysis more efficient.

The programming circuit of SRAM-based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We first derive test procedures for the shift registers, which can be done by using only the faculties of the programming circuit, without using additional hardware. Next, we show the validness of the test procedures. Finally, we show an application of the test procedures to test Xilinx XC4025.

This paper discusses the classification of targets buried in the underground by radar polarimetry. The subsurface radar is used for the detection of objects buried beneath the ground surface, such as gas pipes, cables and cavities, or in archeological exploration operation. In addition to target echo, the subsurface radar receives various other echoes, because the underground is inhomogeneous medium. Therefore, the subsurface radar needs to distinguish these echoes. In order to enhance the discrimination capability, we first applied the polarization anisotropy coefficient to distinguish echoes from isotropic targets (plate, sphere) versus anisotropic targets (wire, pipe). It is straightforward to find the man-made target buried in the underground using the polarization anisotropy coefficient. Second, we tried to classify targets using the polarimetric signature approach, in which the characteristic polarization state provides the orientation angle of an anisotropic target. All of these values contribute to the classification of a target. Field experiments using an ultra-wideband (250 MHz to 1 GHz) FM-CW polarimetric radar system were carried out to show the usefulness of radar polarimetry. In this paper, several detection and classification results are demonstrated. It is shown that these techniques improve the detection capability of buried target considerably.

The ATM Forum specifies several fairness criteria, thus the scheduling mechanisms should allocate enough bandwidth to each connection to achieve one of such fairness criteria. However, two fairness criteria (MCR plus equal share, maximum of MCR or Max-Min share) cannot be achieved by conventional scheduling mechanisms. In this letter, we have developed new scheduling mechanisms that achieve these fairness criteria. We also present simulation results to show that our mechanisms can allocate bandwidth fairly.

This paper treats a fault detection/location of multi-processor systems, and we present a checking scheme based on Modified Processor-Data (MPD) graph with considering an error generation/propagation model for Algorithm-Based Fault Tolerant (ABFT) systems. The error propagation model considered here allows a computation result with multiple (more than one) erroneous inputs to be either erroneous or error-free. Also a basic algorithm for constructing checks for single-fault locatable/two-fault detectable ABFT systems based on the checking scheme is described with design examples.

Secret information stored in a tamperfree device is revealed during the decryption or signature generation processes due to fault-based attack. In this paper, based on the coding approach, we propose a new fault-resistant system which enables any fault existing in modular multiplication and exponentiation computations to be detected with a very high probability. The proposed method can be used to implement all crypto-schemes whose basic operations are modular multiplications for resisting both memory and computational fault-based attacks with a very low computational overhead.

Hawkins noise model is modified for HBT application. The non-ideal ideality factor of HBT is included in both dynamic resistance and noise figure equations. Emitter resistance is also included. The extraction method of noise resistance Rn is developed. Based on the method, a simple analytic equation of Rn is derived and experimentally verified. The effects of noise sources on minimum noise figure are analyzed. The dominant noise sources are the shot noises of emitter and collector currents. Generally, when the minimum noise figure is measured at various current levels, there exists an current level at which the slope of minimum noise figure curve is zero. The zero slope current level coincides with the current level at which the noise contribution of the emitter and collector shot noises including the cancellation by correlation of two sources is minimum. Parasitic resistance degrades output noise through the shot noise amplification with a minor effect of the thermal noise of itself.

In this paper we present a rigorous vector 3D lithography simulator METROPOLE-3D which is designed to run moderately fast on conventional engineering workstations. METROPOLE-3D solves Maxwell's equations rigorously in three dimensions to model how the non-vertically incident light is scattered and transmitted in non-planar structures. METROPOLE-3D consists of several simulation modules: photomask simulator, exposure simulator, post-exposure baking module and 3D development module. This simulator has been applied to a wide range of pressing engineering problems encountered in state-of-the-art VLSI fabrication processes, such as layout printability/manufacturability analysis including reflective notching problems and optimization of an anti-reflective coating (ARC) layer. Finally, a 3D contamination to defect transformation study was successfully performed using our rigorous simulator.

The formulation of the wall admittance of a circular microstrip antenna by the spectral domain method is presented. The circular microstrip antenna is calculated using the cavity model. The electromagnetic fields within the antenna cavity are determined from the impedance boundary condition at the side aperture. The contribution from the region outside the antenna is taken into account by the wall admittance. The wall admittance is defined by the magnetic field produced by the equivalent magnetic current at the aperture. The magnetic field is calculated by the spectral domain method. The wall admittances obtained by this method are compared with the results calculated by Shen. The calculated input impedances of the microstrip antenna agree fairly well with the experimental data for the substrate thickness of up to 0.048λg. The formulation of wall admittance presented here is easily applicable to arbitrarily shaped microstrip antennas.

We propose two fault-tolerant broadcasting schemes in star graphs. One of the schemes can tolerate up to n2 faults of the crash type in the n-star graph. The other scheme can tolerate up to (n3d1)/2 faults of the Byzantine type in the n-star graph, where d is the smallest positive integer satisfying nd!. Each of the schemes is designed for the single-port mode, and it completes the broadcasting in O(n log n) time. These schemes are time optimal. For the former scheme we analyze the reliability in the case where faults of the crash type are randomly distributed. It can tolerate (n!)α faults randomly distributed in the n-star graph with a high probability, where α is any constant less than 1.

In this paper, the Lapped Orthogonal Transform (LOT) with unequal length basis function is considered. The proposed unequal length LOT (ULLOT) has both long basis of length 2M and short basis of length M, while the lengths of all bases of the conventional LOT are 2M. A new class of LOT can be constructed with some modifications of Malvar's Fast LOT. Therefore, the fast algorithm for the Discrete Cosine Transform (DCT) will surely facilitate the computation of the ULLOT. Although the computational complexity of the ULLOT is always lower than that of the LOT, there exist some cases where the coding gain of the ULLOT becomes slightly higher than that of the LOT. Its ability to reduce ringing artifacts is an attractive feature as well. The size-limited structure for the finite length signal is investigated and the ULLOTs are tested on image coding application. The simulation results confirm the validity of the proposed ULLOT.

The self-healing capability against network failure is one of indispensable features for the B-ISDN infrastructure. One problem in realizing such self-healing backbone network is the inefficient utilization of the large spare capacity designed for the failure-restoration purpose since it will be used only in the failure time that does not occur frequently. "Pool-capacity" is the concept that allows some VPs (virtual paths) to efficiently utilize this spare capacity part. Although the total capacity can be saved by using the "Pool Capacity," it is paid by less reliability of VPs caused by the emerging influence of indirect-failure. Thus, this influence of indirect-failure has to be considered in the capacity designing process so that network-designers can trade off the saving of capacity with the reliability level of VPs in their self-healing networks. In this paper, Damage Rate:DR which is the index to indicate the level of the influence caused by indirect-failure is defined and the pool-capacity design scheme with DR consideration is proposed. By the proposed scheme, the self-healing network with different cost (pool-capacity) can be designed according to the reliability level of VPs.

A compact new test structure using shift register circuits for extracting components of the capacitance matrix of the multi-layer interconnections has been proposed. An extraction method of the capacitance matrix is also presented. As a result of fabrication, capacitance values obtained by measurement are in good agreement with the numerical calculation. We also showed an estimation method of the measurement errors.