We exploit a structural knowledge representation scheme called System Entity Structure (SES) methodology to represent and manage wafer failure patterns which can make a significant influence to FABs in the semiconductor industry. It is important for the engineers to simulate various system verification processes by using predefined system entities (e.g., decomposition, taxonomy, and coupling relationships of a system) contained in the SES. For better computational performance, given a certain failure pattern, a Pruned SES (PES) can be extracted by selecting the only relevant system entities from the SES. Therefore, the SES-based simulation system allows the engineers to efficiently evaluate and monitor semiconductor data by i) analyzing failures to find out the corresponding causes and ii) managing historical data related to such failures.

We propose a novel technique of matching at both ends of the guard trace to suppress resonance. This approach is derived from the viewpoint that the guard trace acts as a transmission line. We examined that matched termination suppresses guard-trace resonance through simulating a circuit and measuring radiation. We found from these results that the proposed method enables guard-trace voltages to remain low and hence avoids increases in radiation. In addition, we demonstrated that "matched termination at the far end of the guard trace" could suppress guard-trace resonance sufficiently at all frequencies. We eventually found that at least two vias at both ends of the guard trace and only one matching resistor at the far end could suppress guard-trace resonance. With respect to fewer vias, the method we propose has the advantage of reducing restrictions in the printed circuit board layout at the design stage.

In wireless sensor networks, adversaries can easily launch application layer attacks, such as false data injection attacks and false vote insertion attacks. False data injection attacks may drain energy resources and waste real world response efforts. False vote insertion attacks would prevent reporting of important information on the field. In order to minimize the damage from such attacks, several prevention based solutions have been proposed by researchers, but may be inefficient in normal condition due to their overhead. Thus, they should be activated upon detection of such attacks. Existing detection based solutions, however, does not address application layer attacks. This paper presents a scheme to adaptively counter false data injection attacks and false vote insertion attacks in sensor networks. The proposed scheme consists of two sub-units: one used to detect the security attacks and the other used to select efficient countermeasures against the attacks. Countermeasures are activated upon detection of the security attacks, with the consideration of the current network status and the attacks. Such adaptive countering approach can conserve energy resources especially in normal condition and provide reliability against false vote insertion attacks.

Broadband wireless access networks are promising technology for providing better end user services. For such networks, designing a scheduling algorithm that fairly allocates the available bandwidth to the end users and maximizes the overall network throughput is a challenging task. In this paper, we develop a centralized fair scheduling algorithm for IEEE 802.16 mesh networks that exploits the spatio-temporal bandwidth reuse to further enhance the network throughput. The proposed mechanism reduces the length of a transmission round by increasing the number of non-contending links that can be scheduled simultaneously. We also propose a greedy algorithm that runs in polynomial time. Performance of the proposed algorithms is evaluated by extensive simulations. Results show that our algorithms achieve higher throughput than that of the existing ones and reduce the computational complexity.

A new fast-lock, low-power digital delay-locked loop (DLL) is presented. A subranging searching algorithm is employed to effectively make the loop locked within only four clock cycles. A half-delay circuit is utilized to cut down power consumption. The prototype DLL in a standard 0.13-µm CMOS process operates in the range from 50 MHz to 400 MHz with four clock cycle lock time and consumes 2.379 mW with 1-V supply at 400 MHz clock rate. The measured RMS jitter and peak-to-peak jitter at 400 MHz are 1.586 ps and 16.67 ps, respectively. It occupies an active area of 0.038 mm2.

The fast H∞ filter is developed by one of the authors, and its practical use in industries is expected. This paper derives a linear propagation model of numerical errors in the recursive variables of the fast H∞ filter, and then theoretically analyzes the stability of the filter. Based on the analyzed results, a numerical stabilization method of the fast H∞ filter is proposed with the error feedback control in the backward prediction. Also, the effectiveness of the stabilization method is verified using numerical examples.

Although the topic of multiple-input multiple-output (MIMO) based orthogonal frequency division multiplexing (OFDM) over different fading channels is well investigated, its closed form symbol error rate (SER) expressions and performance results employing orthogonal space time block codes (OSTBCs) over uncorrelated frequency-selective Nakagami-m fading channels are still not available. The closed form expressions are extremely useful for evaluating system's performance without carrying out time consuming simulations. Similarly, the performance results are also quite beneficial for determining the system's performance in the sense that many practical wireless standards extensively employ MIMO-OFDM systems in conjunction with M-ary quadrature amplitude modulation (M-QAM) constellation. This paper thus, derives exact closed form expressions for the SER of M-ary Gray-coded one and two dimensional constellations when an OSTBC is employed and Nt transmit antennas are selected for transmission over frequency-selective Nakagami-m fading channels. For this purpose, first an exact closed-form of average SER expression of OSTBC based MIMO-OFDM system for M-ary phase shift keying (M-PSK) using traditional probability density function (PDF) approach is derived. We then compute exact closed form average SER expressions for M-ary pulse amplitude modulation (M-PAM) and M-QAM schemes by utilizing this generalized result. These expressions are valid over both frequency-flat and frequency-selective Nakagami-m fading MIMO channels and can easily be evaluated without using any numerical integration methods. We also show that average SER of MIMO-OFDM system using OSTBC in case of frequency-selective Rayleigh fading channels remains independent to the number of taps, L of that fading channel and the performance of the same system for two-tap un-correlated Rayleigh and Nakagami-m fading channels is better than that of the correlated one. Moreover, Monte Carlo simulation of MIMO-OFDM system using multiple transmit and receive antennas for different modulations is presented to validate our theoretical results. Finally, due to availability of closed form expressions, we further provide the performance results of MIMO-OFDM system over frequency-selective Nakagami-m fading channels employing (M-QAM) using OSTBCs under the transmission rate equal to 1, 2 and 3 bit(s)/s/Hz, respectively.

In this letter, we study cell cooperation in the downlink OFDMA cellular networks. The proposed cooperation scheme is based on fractional frequency reuse (FFR), where a cooperation group consists of three sector antennas from three adjacent cells and the subchannels of each cooperation group are allocated coordinately to users. Simulation results demonstrate the effectiveness of the proposed schemes in terms of throughput and fairness.

To deal with the increasing number of mobile devices accessing the Internet and the increasing demands of mobility management, IETF has proposed Mobile IPv6 and its fast handover protocol FMIPv6. In FMIPv6, the possibility of Care-of Address (CoA) collision and the time for Return Routability (RR) procedure result in long handover delay, which makes it unsuitable for real-time applications. In this paper, we propose an improved handover scheme for FMIPv6, which reduces the handover delay by using proactive CoA acquisition, configuration and test method. In our proposal, collision-free CoA is proactively prepared, and the time for RR procedure does not contribute to the handover delay. Furthermore, we analyze our proposal's benefits and overhead tradeoff. The numerical results demonstrate that it outperforms the current schemes, such as FMIPv6 and enhanced FMIPv6, on the aspect of handover delay and packet transmission delay.

In this paper we present a study on the design optimization of voltage-controlled oscillators. The phase noise of LC-type oscillators is basically limited by the quality factor of inductors. It has been experimentally shown that higher-Q inductors can be achieved at higher frequencies while the oscillation frequency is limited by parasitic capacitances. In this paper, the minimum transistor size and the degradation of the quality factor caused by a switched-capacitor array are analytically estimated, and the maximum oscillation frequency of VCOs is also derived from an equivalent circuit by considering parasitic capacitances. According to the analytical evaluation, the phase noise of a VCO using a 65 nm CMOS is 2 dB better than that of a 180 nm CMOS.

A method of fault diagnosis was proposed for power electronics circuits based on S transforms similarity. At first, the standard module time-frequency matrixes of S transforms for all fault signals were constructed, then the similarity of fault signals' module time-frequency matrixes to standard module time-frequency matrixes were calculated, and according to the principle of maximum similarity, the faults were diagnosed. The simulation result of fault diagnosis of a thyristor in a three-phase full-bridge controlled rectifier shows that the method can accurately diagnose faults and locate the fault element for power electronics circuits, and it has excellent performance for noise robustness and calculation complexity, thus it also has good practical engineering value in the solution to the fault problems for power electronics circuits.

In this paper, a novel orthogonal frequency-division multiplexing (OFDM) modulator/demodulator based on real-valued discrete Hartley transform (DHT) is presented and implemented for the IEEE 802.11a/g wireless local area network (LAN). Instead of the conventional complex-valued fast Fourier transform (FFT) for OFDM systems, the proposed architecture employs two real-valued fast DHT (FHT) kernels and one post processing unit. By taking advantage of the real-valued operation of FHT, this approach reduces the number of multiplications compared with the radix-2 FFT. The proposed DHT-based modulator/demodulator was designed and fabricated in 0.18-µm CMOS technology with a core area of 928935 µm2. The average power consumption is about 20.16 mW at 20 MHz and 1.8 V supply voltage. Measurement results of the integrated circuit illustrate its superior chip area and power consumption.

Future high-resolution short-range automotive radar will have a higher false alarm probability than the conventional low-resolution radar has. In a high-resolution radar, the reception signal becomes sensitive to the difference between intended and unintended objects. However, automotive radars must distinguish targets from background objects that are the same order of size; it leads to an increase in the false alarm probability. In this paper, a CFAR circuit for obtaining the target mean power, as well as the background mean power, is proposed to reduce the false alarm probability for high-resolution radars working in automotive environments. The proposed method is analytically evaluated with use of the characteristic function method. Spatial correlation is also considered in the evaluation, because the sizes of the both target and background objects approach the dimension of several range cells. Result showed the proposed CFAR with use of two alongside range cells could reduce the ratio of 6.4 dB for an example of an automotive situation.

Automated bug localization is an important issue in software engineering. In the last few decades, various proactive and reactive localization approaches have been proposed to predict the fault-prone software modules. However, most proactive or reactive approaches need source code information or software complexity metrics to perform localization. In this paper, we propose a reactive approach which considers only bug report information and historical revision logs. In our approach, the co-location relationships among bug reports are explored to improve the prediction accuracy of a state-of-the-art learning method. Studies on three open source projects reveal that the proposed scheme can consistently improve the prediction accuracy in all three software projects by nearly 11.6% on average.

With the emergence of bandwidth-greedy application services, high-speed transport protocols are expected to effectively and aggressively use large amounts of bandwidth in current broadband and multimedia networks. However, when high-speed transport protocols compete with other standard TCP flows, they can occupy most of the available bandwidth leading to disruption of service. To deploy high-speed transport protocols on the Internet, such unfair situations must be improved. In this paper, therefore, we propose a method to improve fairness, called Kyushu-TCP (KTCP), which introduces a non-aggressive period in the congestion avoidance phase to give other standard TCP flows more chances of increasing their transmission rates. This method improves fairness in terms of the throughput by estimating the stably available bandwidth-delay product and adjusting its transmission rate based on this estimation. We show the effectiveness of the proposed method through simulations.

An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13 µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100 ns TLP system. From the HBM/ CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1 kV, MM 100 V and CDM 500 V.

To tackle the increasing testing power during built-in self-test (BIST) operations, this paper proposes a new test pattern generator (TPG). With the proposed reconfigurable LFSR, the reconfigurable Johnson counter, the decompressor and the XOR gate network, the introduced TPG can produce the single input change (SIC) sequences with few repeated vectors. The proposed SIC sequences minimize switching activities of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can effectively save test power, and does not impose high impact on test length and hardware for the scan based design.

Design of the 30 nm FinFETs and Double Gate MOSFETs with the halo structure for suppressing the threshold voltage roll-off and improving the subthreshold swing at the same time is proposed for the first time. The performances of nano scale FinFETs and Double Gate MOSFETs with the halo structure are analyzed using a two-dimensional device simulator. The device characteristics, focusing especially on the threshold voltage and subthreshold slope, are investigated for the different gate length, body thickness, and halo impurity concentration. From the viewpoint of body potential control, it is made clear on how to design the halo structure to suppress the short channel effects and improve the subthreshold-slope. It is shown that by introducing the halo structure to FinFETs and Double Gate MOSFETs, nano-scale FinFETs and Double Gate MOSFETs achieve an improved S-factor and suppressed threshold voltage Vth roll-off simultaneously.

In this paper, we propose a new subcarrier allocation algorithm for a downlink OFDMA relay network with multicells. In the proposed algorithm, subcarriers are allocated to users and relays to maximize the overall sum of the achievable rate under fairness constraints. Simulation results show that the proposed algorithm achieves higher data rate than the static algorithm and reduces the outage probability compared to the static and greedy algorithms.

This paper presents a novel cross-layer approach to explore selection diversity for distributed clustering based wireless sensor networks (WSNs) by selecting a proper cluster-head. We develop and analyze an instantaneous channel state information (CSI) based cluster-head selection algorithm for a distributed, dynamic and randomized clustering based WSN. The proposed cluster-head selection scheme is also random and capable to distribute the energy uses among the nodes in the network. We present an analytical approach to evaluate the energy efficiency and system lifetime of our proposal. Analysis shows that the proposed scheme outperforms the performance of additive white Gaussian noise (AWGN) channel under Rayleigh fading environment. This proposal also outperforms the existing cooperative diversity protocols in terms of system lifetime and implementation complexity.