This article proposes a channel estimation method for the downlink channels of a WCDMA system in a high-speed railroad setting. High mobility may cause conventional symbol-level channel estimation to yield severe errors because in conventional methods channel state has to maintain constant within one to several symbol durations. However, in high mobility environment, this assumption may not hold. Errors are particularly more dangerous when using very high spreading factors. In order to counteract the adverse effect of high mobility on channel estimation, we shorten the observation window to that of an N-chip block so that channel conditions or characteristics remain approximately unchanged. We consider channel estimation prior to dispreading the received signal. In other words, channel estimation is done at the chip level rather than the conventional symbol level. The least squares (LS) criterion is employed to acquire channel characteristics for each block of N pilot chips, and the linear interpolation method is used to determine the channel characteristics for each data chip. The LS-based estimator is selected due to its simplicity since it does not need to know channel or noise statistics. An LS-based estimator at the chip level has the further advantage that it is robust against interpath interference (IPI). The uncoded bit error rate (BER) performance of a RAKE receiver using different channel estimation schemes is evaluated and compared through simulations. The proposed scheme is found to be suitable for a high-speed railroad setting.

As the demand for reliable high speed data transmission increases, the capacity of downlink cellular multiple-input multiple-output (MIMO) systems is of much interest. Unfortunately, the capacity analysis regarding the frequency reuse factor (FRF) is rarely reported. In this paper, theoretical analyses for both ergodic and outage capacities for cellular MIMO systems are presented. The FRF is considered and a hybrid frequency reuse scheme is proposed. It is shown by the numerical results that the proposed scheme can greatly alleviate the coverage problem of single-frequency-reuse cellular systems.

We analyze the carrier dynamics in MOSFETs under low-voltage operation. For this purpose the displacement (charging/discharging) current, induced during switching operations is studied experimentally and theoretically for a 90 nm CMOS technology. It is found that the experimental transient characteristics can only be well reproduced in the circuit simulation of low voltage applications by considering the carrier-transit delay in the compact MOSFET model. Long carrier transit delay under the low voltage switching-on operation results in long duration of the displacement current flow. On the other hand, the switching-off characteristics are independent of the bias condition.

Quantum circuits for elementary arithmetic operations are important not only for implementing Shor's factoring algorithm on a quantum computer but also for understanding the computational power of small quantum circuits, such as linear-size or logarithmic-depth quantum circuits. This paper surveys some recent approaches to constructing efficient quantum circuits for elementary arithmetic operations and their applications to Shor's factoring algorithm. It covers addition, comparison, and the quantum Fourier transform used for addition.

This letter investigates a subchannel and power allocation (SPA) algorithm which maximizes the throughput of a user under the constraints of total transmit power and fair subchannel occupation among relay nodes. The proposed algorithm reduces computational complexity from exponential to linear in the number of subchannels at the expense of a small performance loss.

A simple exact error rate analysis is presented for random binary direct sequence code division multiple access (DS-CDMA) considering a general pulse shape and flat Nakagami fading channel. First of all, a simple model is developed for the multiple access interference (MAI). Based on this, a simple exact expression of the characteristic function (CF) of MAI is developed in a straight forward manner. Finally, an exact expression of error rate is obtained following the CF method of error rate analysis. The exact error rate so obtained can be much easily evaluated as compared to the only reliable approximate error rate expression currently available, which is based on the Improved Gaussian Approximation (IGA).

Fair allocation of bandwidth and maximization of channel utilization are two important issues when designing a contention-based wireless medium access control (MAC) protocol. However, fulfilling both design goals at the same time is very difficult. Considering the problem in the IEEE 802.11 wireless local area networks (WLANs), in this work we propose a method using a p-persistent enhanced DCF, called P-IEEE 802.11 DCF, to achieve weighted fairness and efficient channel utilization among multiple priority classes in a WLAN. Its key idea is that when the back-off timer of a node reaches zero, the transmission probability is properly controlled to reflect the relative weights among data traffic flows so as to maximize the aggregate throughput and to minimize the frame delay at the same time. In particular, we obtain the optimal transmission probability based on a theoretical analysis, and also provide an approximation to this probability. The derived optimal and approximation are all evaluated numerically and simulated with different scenarios. The results show that the proposed method can fulfill our design goals under different numbers of priority classes and different numbers of nodes.

Testing and diagnosis techniques play a key role in the advance of semiconductor memory technology. The challenge of failure detection has created intensive investigation on efficient testing and diagnosis algorithm for better fault coverage and diagnostic resolution. At present, March test algorithm is used to detect and diagnose all faults related to Random Access Memories. However, the test and diagnosis process are mainly done manually. Due to this, a systematic approach for developing and evaluating memory test algorithm is required. This work is focused on incorporating the March based test algorithm using a software simulator tool for implementing a fast and systematic memory testing algorithm. The simulator allows a user through a GUI to select a March based test algorithm depending on the desired fault coverage and diagnostic resolution. Experimental results show that using the simulator for testing is more efficient than that of the traditional testing algorithm. This new simulator makes it possible for a detailed list of stuck-at faults, transition faults and coupling faults covered by each algorithm and its percentage to be displayed after a set of test algorithms has been chosen. The percentage of diagnostic resolution is also displayed. This proves that the simulator reduces the trade-off between test time, fault coverage and diagnostic resolution. Moreover, the chosen algorithm can be applied to incorporate with memory built-in self-test and diagnosis, to have a better fault coverage and diagnostic resolution. Universities and industry involved in memory Built-in-Self test, Built-in-Self repair and Built-in-Self diagnose will benefit by saving a few years on researching an efficient algorithm to be implemented in their designs.

We propose an appearance manifold with view-dependent covariance matrix for face recognition from video sequences in two learning frameworks: the supervised-learning and the incremental unsupervised-learning. The advantages of this method are, first, the appearance manifold with view-dependent covariance matrix model is robust to pose changes and is also noise invariant, since the embedded covariance matrices are calculated based on their poses in order to learn the samples' distributions along the manifold. Moreover, the proposed incremental unsupervised-learning framework is more realistic for real-world face recognition applications. It is obvious that it is difficult to collect large amounts of face sequences under complete poses (from left sideview to right sideview) for training. Here, an incremental unsupervised-learning framework allows us to train the system with the available initial sequences, and later update the system's knowledge incrementally every time an unlabelled sequence is input. In addition, we also integrate the appearance manifold with view-dependent covariance matrix model with a pose estimation system for improving the classification accuracy and easily detecting sequences with overlapped poses for merging process in the incremental unsupervised-learning framework. The experimental results showed that, in both frameworks, the proposed appearance manifold with view-dependent covariance matrix method could recognize faces from video sequences accurately.

We propose a Solid-State Disk (SSD) with a Double Data Rate (DDR) DRAM interface for high-performance PCs. Traditional SSDs simply inherit the interface protocol of Hard Disk Drives (HDD) such as Parallel Advanced Technology Attachment (PATA) or Serial-ATA (SATA) for maintaining the compatibility. However, SSD itself provides much higher performance than HDD, hence the interface also needs to be enhanced. Unlike the traditional SSDs, the proposed SSD with DDR DRAM interface is placed in the North Bridge which provides two or more DDR DRAM interface ports in high-performance PCs. The novelty of our work is on DQS signaling scheme which allows arbitrary Column Address Strobe (CAS) latency unlike typical DDR DRAM interface scheme. The experimental results show that the proposed SSD maximally outperforms the traditional SSD by 8.7 times in read mode, by 1.5 times in write mode. Also, for synthetic workloads, the proposed scheme shows performance improvement over the conventional architecture by a factor of 1.6 times.

A new hierarchical isosurface reconstruction scheme from a set of tomographic cross sectional images is presented. From the input data, we construct a hierarchy of volume, called the volume pyramid, based on a 3D dilation filter. After extracting the base mesh from the volume at the coarsest level by the cell-boundary method, we iteratively fit the mesh to the isopoints representing the actual isosurface of the volume. The SWIS (Shrink-wrapped isosurface) algorithm is adopted in this process, and a mesh subdivision scheme is utilized to reconstruct fine detail of the isosurface. According to experiments, our method is proved to produce a hierarchical isosurface which can be utilized by various multiresolution algorithms such as interactive visualization and progressive transmission.

A PN junction current model for advanced MOSFETs is proposed and implemented into HiSIM2, a complete surface-potential-based MOSFET model. The model includes forward diode currents and reverse diode currents, and requires a total of 13 model parameters covering all bias conditions. Model simulation results reproduce measurements for different device geometries over a wide range of bias and temperature values.

The recognition performance of the conventional 3D face recognition algorithm using ICP (Iterative Closest Point) is degraded for the 3D face data with expression changes. Addressing this problem, we consider the use of the expression-invariant local regions of a face. We find the expression-invariant regions through the distance analysis between 3D face data with the neutral expression and smile, and propose a robust 3D face recognition algorithm using passive stereo vision. We demonstrate efficient recognition performance of the proposed algorithm compared with the conventional ICP-based algorithm through the experiment using a stereo face image database which includes the face images with expression changes.

Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.

In this letter, we derive an exact bit error rate (BER) expression for downlink multi-carrier code division multiple access (MC-CDMA) systems with orthogonal restoring combining (ORC) in Nakagami-m fading channel. A simple approximated expression is also provided. For uncoded and coded MC-CDMA systems, the BER expressions are calculated based on the moment generating function (MGF) of the combined fading random variable. The derived analytic expressions are verified by simulation results.

This paper describes new DDRx SDRAM interface architecture suitable for system-on-chip (SOC) implementation. Our test chip fabricated in a 90-nm CMOS process adopts three key schemes and achieves 960 Mb/s/pin operations with 32 bits width. One of new schemes is to suppress timing skew with rising-edge signal transmission I/O circuit and look-up table type impedance calibration circuit. DQS round-trip-time, propagation delay from rising edge of system clock in SOC to arrival of DQS at input PAD of SOC during read operation, becomes longer than one clock cycle time as for DDR2 interface and beyond. Flexible DQS round-trip-time scheme can allow wide range up to N/2 cycles in N bits burst read operation. In addition, full self loop-backed test scheme is also proposed to measure AC timing parameters without high-end tester. The architecture reported in this paper can be continuously adaptive to realize higher data-rate and cost-efficient DDRx-SDRAM interface for various kinds of SOC.

Nonnegative matrix factorization (NMF) and its extensions such as Nonnegative Tensor Factorization (NTF) have become prominent techniques for blind sources separation (BSS), analysis of image databases, data mining and other information retrieval and clustering applications. In this paper we propose a family of efficient algorithms for NMF/NTF, as well as sparse nonnegative coding and representation, that has many potential applications in computational neuroscience, multi-sensory processing, compressed sensing and multidimensional data analysis. We have developed a class of optimized local algorithms which are referred to as Hierarchical Alternating Least Squares (HALS) algorithms. For these purposes, we have performed sequential constrained minimization on a set of squared Euclidean distances. We then extend this approach to robust cost functions using the alpha and beta divergences and derive flexible update rules. Our algorithms are locally stable and work well for NMF-based blind source separation (BSS) not only for the over-determined case but also for an under-determined (over-complete) case (i.e., for a system which has less sensors than sources) if data are sufficiently sparse. The NMF learning rules are extended and generalized for N-th order nonnegative tensor factorization (NTF). Moreover, these algorithms can be tuned to different noise statistics by adjusting a single parameter. Extensive experimental results confirm the accuracy and computational performance of the developed algorithms, especially, with usage of multi-layer hierarchical NMF approach [3].

Recently, there has been growing interest in the design of wireless cooperative protocol to achieve higher diversity-multiplexing tradeoff among single antenna devices. We propose an automatic request for cooperation (ARC) scheme for wireless networks which can achieve higher order diversity by selecting the best relay. In this scheme, a source transmits a data packet towards a destination and a group of relays. The destination tries to decode the information from the source and if the detection is correct the process will stop. Otherwise, the destination transmits an ARC towards the relays. We utilize this ARC signal for selecting the best relay from the set of relays that have successfully decoded the source packet. The selected relay generates and transmits redundant information for the source packet. The destination combines the two packets received from the source and the best relay to improve the reliability of the packet. We analyze the packet error rate, spectral efficiency and diversity-multiplexing tradeoff of our proposal and compare them with some existing protocols. Analysis shows that our proposal can achieve higher diversity multiplexing tradeoff than conventional cooperative protocols.

Two discrete-time Wirtinger-type inequalities relating the power of a finite-length signal to that of its circularly-convolved version are developed. The usual boundary conditions that accompany the existing Wirtinger-type inequalities are relaxed in the proposed inequalities and the equalizing sinusoidal signal is free to have an arbitrary phase angle. A measure of this sinusoidal signal's power, when corrupted with additive noise, is proposed. The application of the proposed measure, calculated as a ratio, in the evaluation of the power of a sinusoid of arbitrary phase with the angular frequency π/N, where N is the signal length, is thoroughly studied and analyzed under additive noise of arbitrary statistical characteristic. The ratio can be used to gauge the power of sinusoids of frequency π/N with a small amount of computation by referring to a ratio-versus-SNR curve and using it to make an estimation of the noise-corrupted sinusoid's SNR. The case of additive white noise is also analyzed. A sample permutation scheme followed by sign modulation is proposed for enlarging the class of target sinusoids to those with frequencies M π/N, where M and N are mutually prime positive integers. Tandem application of the proposed scheme and ratio offers a simple method to gauge the power of sinusoids buried in noise. The generalization of the inequalities to convolution kernels of higher orders as well as the simplification of the proposed inequalities have also been studied.

In this paper, we consider a dual-hop wireless cooperative network with amplify-and-forward (AF) relaying. The output signal-to-noise ratio (SNR) at the destination of the AF cooperative networks is in the form of the sum of harmonic mean of the source-relay channel SNR and the relay-destination channel SNR. Instead of deriving the exact probability density function (PDF) of the output SNR, we study the series expansion of this PDF around zero. This result is then applied to evaluate the performance of the AF cooperative systems over Nakagami-m fading channels, and closed-form high-SNR approximations of the average symbol error rate (SER) and the outage probability are derived. Next, we investigate the optimal power allocation (OPA) among the source node and the relays to minimize the approximate SER as well as the outage probability. It is shown that the optimal power allocation depends on the channel m parameters and the ratio of the source-relay channel gain to the relay-destination gain. In addition to the optimal power allocation, we also propose a low complexity sub-optimal power allocation (SubOPA) scheme. The performance improvement with optimal and sub-optimal power allocation is analyzed and validated by numeric results. It is shown that equal power allocation is near optimal when the relays are close to the source, while significant performance improvement is observed by both the optimal and sub-optimal power allocation schemes when the relays are close to the destination.