This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The NN matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N2 to (N/D)2. Each block contains N/D input lines and N/D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N/D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of 10-8 is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit/s high-speed ATM switch fabric needed for B-ISDN.

Since semiconductor memory chip has been growing rapidly in its capacity, memory testing has become a crucial problem in RAMs. This paper proposes a new RAM test algorithm, called generalized marching test (GMT), which detects static and dynamic pattern sensitive faults (PSF) in RAM chips. The memory array with N cells is partitioned into B sets in which every two cells has a cell-distance of at least d. The proposed GMT performs the ordinary marching test in each set and finally detects PSF having cell-distance d. By changing the number of partitions B, the GMT includes the ordinary marching test for B1 and the walking test for BN. This paper demonstrates the practical GMT with B2, capable of detecting PSF, as well as other faults, such as cell stuck-at faults, coupling faults, and decoder faults with a short testing time.

This system called COKIS automatically extracts knowledge about C functions from the UNIX on-line manual by using its description paragraph and the user can interactively inquire to the system in order to know about UNIX C functions. The idea is motivated on the one side to free users from being involved in an exhaustive knowledge acquisition in the past, and to examine problems in understanding knowledge itself on the other. We propose Memory Processor which is implemented to realize extracting knowledges from corpus and processing dialogues in the inquiry system at the same modules.

A novel external clocking magnetic disk recording channel is proposed and examined. Timing not only for data recovery but for recording is given by a bit clock which is synchronized with dedicated clock marks on patterned discrete track media. Jitter of the bit clock is 2.5 ns (rms), which is good enough for data rates up to about 20 Mbit/s. Using an MR/Inductive head and PRML (Partial Response Maximum Likelihood) signal processing, an error rate of 110-6 is obtained at linear density 3146 bit/mm.

Recently, studies aiming at the next generation of visual communication services which support better human communication have been carried out intensively in Japan. The principal motive of these studies is to develop new services which are not restricted to a conventional communication framework based on the transmission of waveform signals. This paper focuses on three important key words in these studies; "intelligent," "real," and "distributed and collaborative," and describes recent research activities. The first key word "intelligent" relates to intelligent image coding. As a particular example, model-based coding of moving facial images is discussed in detail. In this method, shape change and motion of the human face is described by a small number of parameters. This feature leads to the development of new applications such as very low bit-rate transmission of moving facial images, analysis and synthesis of facial expression, human interfaces, and so on. The second key word "real" relates to communication with realistic sensations and virtual space teleconferencing. Among various component technologies, real-time reproduction of 3-D human images and a cooperative work environment with virtual space are discussed in detail. The last key word "distributed and collaborative" relates to collaborative work in a distributed work environment. The importance of visual media in collaborative work, a concept of CSCW, and requirements for realizing a distributed collaborative environment are discussed. Then, four examples of CSCW systems are briefly outlined.

In the applications of the fast Fourier transform (FFT) to real-world computation such as robot vision, high-speed processing with small latency is an important issue. In this paper, we propose a linear array processor for the minimum-latency FFT computation. The processor is constructed by identical butterfly elements (BE's). The key concept to minimize the latency is that each BE generates its output data immediately after its input data become available, with 100% utilization of its arithmetic unit. We also introduce the real-valued FFT to perform the complex-valued FFT. We utilize a double linear array structure so that the parallel processing can be realized without communication between the linear arrays. As a result, the hardware amount of a single BE is reduced to half that of conventional designs. The latency of the proposed FFT processor is greatly reduced in comparison with conventional linear array FFT processors.

The Viterbi algorithm is a well-established technique for channel and source decoding in high performance digital communication systems. However, excessive time consumption makes it difficult to design an efficient high-speed decoder for practical application. This paper describes the implementation of parallel Viterbi algorithm by multi-microprocessors. Internal computations are performed in a parallel fashion. The use of microprocessors allows low-cost implementation with moderate complexity. The software and hardware implementations of the Viterbi algorithm on parallel multi-microprocessors for real-time decoding are presented. The implemented method is based on a combination of forming a set of tables and calculations. For efficient operation under fully parallel Viterbi decoding by microprocessors, we considered: (1) branch metrics processing, path metrics updating, path memory updating and decoding output for microprocessor, (2) efficient decomposition of the sequential Viterbi algorithm into parallel algorithms, (3) minimization of the communication among the microprocessors. The practical solutions for the problems of synchronization among the miroprocessors, interconnection network for communication among the microprocessors and memory management are discussed. Furthermore the performance and the speed of the parallel Viterbi decoding are given. For a fixed processing speed of given hardwares, parallel Viterbi decoding allows a linear speed up in the throughput rate with a linear increase in hardware complexity.

The generation mechanism for excess intensity noise due to optical feedback is analyzed theoretically and experimentally. Modal rate equations under the weakly coupled condition with external feedback are derived to include the mode competition phenomena in DFB and Fabry-Perot lasers. We found that the sensitivity of the external feedback strongly depends on design parameters of structure, such as the coupling constant of the corrugation, the facet reflection and the phase relation between the corrugation and the facet. A DFB laser whose oscillating wavelength is well adjusted to Bragg wavelength through insertion of a phase adjustment region becomes less sensitive to external optical feedback than a Fabry-Perot laser, but other types of DFB lasers revealing a stop band are more sensitive than the Fabry-Perot laser.

This paper describes the characteristics and application of lumped double crosstie slow-wave transmission lines (DCT-SLWs) which we previously proposed. Firstly, the relationship between the DCT-SLW's characteristics and their parameters, i. e. triplate stripline widths and inductor resistances, are numerically and experimentally investigated. Excellent slow-wave lines with both high slow-wave factors (1240) and a wide characteristic impedance range (35100Ω) are achieved in good agreement with calculated results. A 50-Ω DCT-SLW that reduces circuit area more than 80%, and has an insertion loss less than that of 22-µm-wide TFMS lines is achieved by adapting a low-loss inductor in the frequencies below 14.5 GHz. Secondly, the application of DCT-SLW to non-dispersive, dispersive delay lines and branch-line hybrids is discussed. Specifically, very small 4-GHz-band branch-line hybrids are fabricated in a chip area of 0.7 mm2. Fundamental microwave circuits utilizing slow-wave lines in MMICs are demonstrated for the first time.

A systematic method is proposed to generate a random image with a known correlation function and the modified Laplace distribution; the modified Laplace distribution includes the one-side exponential distribution and the Laplace distribution as a special case. Several random images with an isotropic correlation and the modified Laplace distribution are generated and displayed in figures.

This paper describes the fundamental principle of novel push-push oscillators using hairpin-shaped split-ring resonators and their application to voltage controlled and injection locked oscillators for frequency synthesizers. The experimental results make it clear that the synthesizer systems discussed here have the advantages of high frequency operation, compact size and low power consumption. Experimental work has been carried out in the L band, but these systems can be applied to much higher frequencies.

Algorithms for computing channel capacity have been proposed by many researchers. Recently, one of the authors proposed an efficient algorithm using Newton's method. Since this algorithm has local quadratic convergence, it is advantageous when we want to obtain a numerical solution with high accuracy. In this letter, it is shown that this algorithm can be extended to the algorithm for computing the constrained capacity, i.e., the capacity of discrete memoryless channels with linear constraints. The global convergence of the extended algorithm is proved, and its effectiveness is verified by numerical examples.

This paper presents ceramic multi-layer substrates for mobile communication using alumina-glass composite ceramics and co-fired copper conductors. Electrical characteristics in GHz frequencies of the substrate, copper conductor, transmission line, via hole and coupling between the striplines were evaluated. The results showed that the ceramic multi-layer substrate had good electrical characteristics enough for GHz-band applications. Using the ceramic multi-layer substrates, one can drastically reduce the size of RF circuit boards for mobile communication equipment.

Existing algorithmic debugging methods which can locate faults under the guidance of a system have a number of shortcomings. For example, some cannot be applied to imperative languages with side effects; some can locate a faulty function but cannot locate a faulty statement; and some cannot detect faults related to missing statements. This paper presents an algorithmic critical slice-based fault-locating method for imperative languages. Program faults are first classified into two categories: wrong-value faults and missing-assignment faults. The critical slice with respect to a variable-value error is a set of statements such that (1) a wrong-value fault contained in any instruction in the critical slice may have caused that variable-value error, and (2) a wrong-value fault contained in any instruction outside the critical slice could never have caused that variable-value error. The paper also classifies errors found during program testing into three categories: wrong-output errors, missing-output errors, and infinite-loop errors with no output. It finally shows that it is possible to algorithmically locate any fault, including missing statements, for each type of error.

A cyclic analog-to-digital (A/D) converter is developed which accomplishes an n-b conversion in n/2 clock cycles. The architecture consists of two 1-b quantizers connected in a loop. A CMOS design of the 1-b quantizer is given to evaluate the performance of the A/D converter when implemented using presently available process. Spice simulations and error analyses show that a resolution higher than 10-b and a sampling rate up to 1.4 Msps are attainable with a 3-µm CMOS process. A prototype converter breadboarded using discrete components has confirmed the principles of operation and error analyses. The device count and the power consumption are small compared to those of a successive-approximation A/D converter. A chip area required for the CMOS implementation is also small because only four unit capacitors are involved. Therefore, the architecture proposed herein is most suited for high accuracy, medium speed A/D conversion.

High-speed learning of neural networks using the multifrequency oscillation method is demonstrated for first time. During the learning of an analog neural network integrated circuit implementing the exclusive-OR' logic, weight and threshold values converge to steady states within 2 ms for a learning speed of 2 mega-patterns per second.

We describe an approach for modelling a person's face for model-based coding. The goal is to estimate the 3D shape by combining the contour analysis and shading analysis of the human face image in order to increase the quality of the estimated 3D shape. The motivation for combining contour and shading cues comes from the observation that the shading cue leads to severe errors near the occluding boundary, while the occluding contour cue provides incomplete surface information in regions away from contours. Towards this, we use the deformable model as the common level of integration such that a higher-quality measurement will dominate the depth estimate. The feasibility of our approach is demonstrated using a real facial image.

The performance evaluation by analysis of systems employing Reduced State Viterbi decoding is addressed. This type of decoding is characterized by an inherent error propagation effect, which yields a difficulty in the error probability analysis, and has been usually neglected in the literature. By modifying the Full State trellis diagram, we derive for Reduced State schemes, new transfer function bounds with the effects of error propagation. Both the Chernoff and the tight upper bound are applied to the transfer function in order to obtain the bit error probability upper bound. Furthermore, and in order to get a tighter bound for Reduced State decoding schemes with parallel transitions, the pairwise probability of the two sequences involved in an error event is upper bounded, and then the branch metric of a sequence taken from that bound is associated with a truncated instead of complete Gaussian noise probability density function. To support the analysis, particular assessment is done for a Trellis Coded Modulation scheme.

This paper presents a new high-speed three-dimensional (3-D) object recognition system based on two-dimensional (2-D) chain code matching. An observed 3-D object is precisely represented by a 2-D chain code sequence from the discrete surface points of the 3-D object, so that any complex objects can be recognized precisely. Moreover, the normalization procedures such as translation, rotation of 3-D objects except scale changes can be performed systematically and regularly regardless of the complexity of the shape of 3-D objects, because almost all the normalization procedures of 3-D objects are included in the 2-D chain code matching procedure. As a result, the additional normalization procedure become only the processing time for scale changes which can be performed easily by normalizing the length of the chain code sequence. In addition, the fast fourier transformation (FFT) is applicable to 2-D chain code matching which calculates cross correlation between an input object and a reference model, so that very fast recognition is performed. In fact, it is demonstrated that the total recognition time of a 3-D ofject is estimated at 5.35 (sec) using the 28.5-MIPS SPARC workstation.

A superresolution technique is considered for use in antenna gain measurements. A modification of the MUSIC algorithm is employed to resolve incident signals separately in the time domain. The modification involves preprocessing the received data using a spatial scheme prior to applying the MUSIC algorithm. Interference rejection in the antenna measurements using the fast Fourier transform (FFT) based techniques have been realized by a recently developed vector network analyzer, and its availability has been reported in the literature. However, response resolution in the time domain of these conventional techniques is limited by the antenna bandwidth. The MUSIC algorithm has the advantage of being able to eliminate unwanted responses when performing antenna measurements in situations where the antenna band-width is too narrow to support FFT based techniques. In this paper, experimental results of antenna gain measurements in a multipath environment show the accuracy and resolving power of this technique.