This paper deals with the uniqueness of a solution of the basic equation obtained from the analysis of resistive circuits including ideal diodes. The equation in consideration is of the type of (A-)X=b, where A is a constant matrix, b a constant vector, X an unknown vector satisfying X 0, and a diagonal matrix whose diagonal elements take the value 0 or 1 arbitrarily. The necessary and sufficient conditions for the equation to have a unique solution X 0 for an arbitrary vector b are shown. Some numerical examples are given for the illustration of the result.

Oversampled analog-to-digital (A/D) converters based on sigma-delta (ΣΔ) modulation are attractive for VLSI implementation because they are especially tolertant of circuit nonidealities and component mismatch. Oversampled ΣΔ modulator has some points which must be improved. Some of these problems are based on the small input signal and the integrator leak. In this paper,ΣΔ A/D converter having a dither circuit to improve the linearity and the compensation technique of the integer leak are presented. By the simulation, the most suitable dither to improve the linearity of the modulator is obtained as follows: the amplitude is 1/150 of input signal maximum amplitude, the frequency is 4-times of the signal-band. Using the compensation circuit of the integrator leak, 72 dB of dynamic range is obtained when op-amp gain is 30 dB.

Switched-current (SI) is a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. In this paper, new switched-current (SI) mirrors using OTAs (operational transconductance amplifiers) are proposed. These circuits are less sensitive to clock-feedthrough noise than conventional SI mirrors by virtue of linear I-V/V-I transformations. In addition, the current gain of the proposed mirror is electronically tunable. Not only inverting mirrors but also noninverting mirrors can be realized by this method.

This paper presents a hardware architecture design methodology for hidden markov model based recognition systems. With the aim of realizing more advanced and user-friendly systems, an effective architecture has been studied not only for decoding, but also learning to make it possible for the system to adapt itself to the user. Considering real-time decoding and the efficient learning procedures, a bi-directional ring array processor is proposed, that can handle various kinds of data and perform a large number of computations efficiently using parallel processing. With the array architecture, HMM sub-algorithms, the forward-backward and Baum-Welch algorithms for learning and the Viterbi algorithm for decoding, can be performed in a highly parallel manner. The indispensable HMM implementation techniques of scaling, smoothing, and estimation for multiple observations can be also carried out in the array without disturbing the regularity of parallel processing. Based on the array processor, we propose the configuration of a system that can realize all HMM processes including vector quantization. This paper also describes that a high PE utilization efficiency of about 70% to 90% can be achieved for a practical left-to-right type HMMs.

The goal of visual telecommunication has been to create a sense of "being there" or "telepresence." This paper introduces a novel shared drawing medium called ClearBoard that goes beyond "being there" by providing virtual shared workspace. It realizes (1) a seamless integration of shared drawing space and partner's image, and (2) eye contact to support real-time and remote collaboration by two users. We devised the key metaphor: "talking through and drawing on a transparent glass window" to design ClearBoard. A prototype, ClearBoard-1 is implemented based on the "Drafter-Mirror" architecture. This paper first reviews previous work on shared drawing support to clarify our design goals. We then examine three metaphors that fulfill these goals. The design requirements and the two possible system architectures of ClearBoard are described. Finally, some findings gained through the experimental use of the prototype, including the feature of "gaze awareness," are discussed.

Manipulation of Boolean functions is one of the most important techniques for implementing of VLSI logic design systems. This paper presents a fast method for generating prime-irredundant covers from Binary Decision Diagrams (BDDs), which are efficient representation of Boolean functions. Prime-irredundant covers are forms in which each cube is a prime implicant and no cube can be eliminated. This new method generates compact cube sets from BDDs directly, in contrast to the conventional cube set reduction algorithms, which commonly manipulate redundant cube sets or truth tables. Our method is based on the idea of a recursive operator, proposed by Morreale. Morreale's algorithm is also based on cube set manipulation. We found that the algorithm can be improved and rearranged to fit BDD operations efficiently. The experimental results demonstrate that our method is efficient in terms of time and space. In practical time, we can generate cube sets consisting of more than 1,000,000 literals from multi-level logic circuits which have never previously been flattened into two-level logics. Our method is more than 10 times faster than ESPRESSO in large-scale examples. It gives quasi-minimum numbers of cubes and literals. This method should find many useful applications in logic design systems.

High-speed learning of neural networks using the multifrequency oscillation method is demonstrated for first time. During the learning of an analog neural network integrated circuit implementing the exclusive-OR' logic, weight and threshold values converge to steady states within 2 ms for a learning speed of 2 mega-patterns per second.

This paper presents ceramic multi-layer substrates for mobile communication using alumina-glass composite ceramics and co-fired copper conductors. Electrical characteristics in GHz frequencies of the substrate, copper conductor, transmission line, via hole and coupling between the striplines were evaluated. The results showed that the ceramic multi-layer substrate had good electrical characteristics enough for GHz-band applications. Using the ceramic multi-layer substrates, one can drastically reduce the size of RF circuit boards for mobile communication equipment.

A cyclic analog-to-digital (A/D) converter is developed which accomplishes an n-b conversion in n/2 clock cycles. The architecture consists of two 1-b quantizers connected in a loop. A CMOS design of the 1-b quantizer is given to evaluate the performance of the A/D converter when implemented using presently available process. Spice simulations and error analyses show that a resolution higher than 10-b and a sampling rate up to 1.4 Msps are attainable with a 3-µm CMOS process. A prototype converter breadboarded using discrete components has confirmed the principles of operation and error analyses. The device count and the power consumption are small compared to those of a successive-approximation A/D converter. A chip area required for the CMOS implementation is also small because only four unit capacitors are involved. Therefore, the architecture proposed herein is most suited for high accuracy, medium speed A/D conversion.

A superresolution technique is considered for use in antenna gain measurements. A modification of the MUSIC algorithm is employed to resolve incident signals separately in the time domain. The modification involves preprocessing the received data using a spatial scheme prior to applying the MUSIC algorithm. Interference rejection in the antenna measurements using the fast Fourier transform (FFT) based techniques have been realized by a recently developed vector network analyzer, and its availability has been reported in the literature. However, response resolution in the time domain of these conventional techniques is limited by the antenna bandwidth. The MUSIC algorithm has the advantage of being able to eliminate unwanted responses when performing antenna measurements in situations where the antenna band-width is too narrow to support FFT based techniques. In this paper, experimental results of antenna gain measurements in a multipath environment show the accuracy and resolving power of this technique.

The performance of processing elements can be improved by the progress of VLSI circuit technology, while the communication overhead can not be negligible in parallel processing system. This paper presents a unified scheduling that allocates tasks having different task processing times in multiple processing elements. The objective function is formulated to measure communication time between processing elements. By employing constraint conditions, the scheduling efficiently generates an optimal solution using an integer programming so that minimum communication time can be achieved. We also propose a VLSI processor for robotics whose latency is very small. In the VLSI processor, the data transfer between two processing elements can be done very quickly, so that the communication cycle time is greatly reduced.

In this paper, we discuss to the intermedia synchronization problems for high speed multimedia communication. Especially, we described how software synchronization can be operated, and estimated the skew bound in CNV when considering the network delay. And we applied CNV to the intermedia synchronization and a hybrid model (HSM) is proposed. Furthermore, we used the statistical approach to evaluate the performance of the synchronization mechanisms. The results of performance evaluation show that HSM has good performance in the probability of estimation error.

In this paper, the characteristics of microstrip lines near the edge of dielectric substrate are analyzed by improving the rectangular boundary division method. The numerical results indicate the changes of the characteristics of a microstrip line when the strip conductor is closely located to the edge. When the distance the dielectric substrate edge to the strip conductor is less than the thickness of dielectric substrate, the effects of the edge on the line characteristics are no longer negligible. The numerical results in this paper show high computation accuracy without increasing computation time. Our improvement is effective for the analysis of the microstrip lines both for the narrow strip conductor and the strip conductor close to the edge. The relative errors between the numerical results and the measured values are less than 1.2%.

In the field of computer vision the detection of edges in an image serves to simplify the date in the early stages, into a form which is more easily processed by the computer. But because of noise or due to the inherent weaknesses of the chosen edge detector, gaps or interruptions in the edges may be formed. In order for further processing to proceed with accuracy and confidence, these gaps must be filled or linked to form a more continuous edge. Proposed in this paper is a unique method of edge linking. This method consists of three steps, labelling, linking and merging. The procedure makes use of global information in the labelling process and local information with the use of templates in the linking and merging processes. As a result of the unique way in which the gaps between edge segments are filled, distortion of the edge image is kept minimal. One other advantage of the proposed edge linker is that it can be used in combination with different edge detection schemes. To show the effectiveness of the proposed method, comparisons are given. These include the linear feature extraction method of Zhou et.al., upon which the proposed method is based and also outputs from a method described by Nevatia.

The Viterbi algorithm is a well-established technique for channel and source decoding in high performance digital communication systems. However, excessive time consumption makes it difficult to design an efficient high-speed decoder for practical application. This paper describes the implementation of parallel Viterbi algorithm by multi-microprocessors. Internal computations are performed in a parallel fashion. The use of microprocessors allows low-cost implementation with moderate complexity. The software and hardware implementations of the Viterbi algorithm on parallel multi-microprocessors for real-time decoding are presented. The implemented method is based on a combination of forming a set of tables and calculations. For efficient operation under fully parallel Viterbi decoding by microprocessors, we considered: (1) branch metrics processing, path metrics updating, path memory updating and decoding output for microprocessor, (2) efficient decomposition of the sequential Viterbi algorithm into parallel algorithms, (3) minimization of the communication among the microprocessors. The practical solutions for the problems of synchronization among the miroprocessors, interconnection network for communication among the microprocessors and memory management are discussed. Furthermore the performance and the speed of the parallel Viterbi decoding are given. For a fixed processing speed of given hardwares, parallel Viterbi decoding allows a linear speed up in the throughput rate with a linear increase in hardware complexity.

Recently, studies aiming at the next generation of visual communication services which support better human communication have been carried out intensively in Japan. The principal motive of these studies is to develop new services which are not restricted to a conventional communication framework based on the transmission of waveform signals. This paper focuses on three important key words in these studies; "intelligent," "real," and "distributed and collaborative," and describes recent research activities. The first key word "intelligent" relates to intelligent image coding. As a particular example, model-based coding of moving facial images is discussed in detail. In this method, shape change and motion of the human face is described by a small number of parameters. This feature leads to the development of new applications such as very low bit-rate transmission of moving facial images, analysis and synthesis of facial expression, human interfaces, and so on. The second key word "real" relates to communication with realistic sensations and virtual space teleconferencing. Among various component technologies, real-time reproduction of 3-D human images and a cooperative work environment with virtual space are discussed in detail. The last key word "distributed and collaborative" relates to collaborative work in a distributed work environment. The importance of visual media in collaborative work, a concept of CSCW, and requirements for realizing a distributed collaborative environment are discussed. Then, four examples of CSCW systems are briefly outlined.

A dielectric rod waveguide applicator for microwave heating such as microwave hyperthermia is described. The applicator consists of the acrylic cylinder filled with deionized water. By circulating the deionized water, the dielectric rod waveguide applicator acts as a surface cooling device, so that it doesn't need any bolus. This surface cooling device enables the dielectric rod waveguide applicator to control the site of effective heating region along the depth axis. Useful pattern of the circular or spheroidal shape and axially symmetric effective heating region were obtained. Furthermore metal strips provided on the aperture of applicator control the shape of the heating pattern.

The performance evaluation by analysis of systems employing Reduced State Viterbi decoding is addressed. This type of decoding is characterized by an inherent error propagation effect, which yields a difficulty in the error probability analysis, and has been usually neglected in the literature. By modifying the Full State trellis diagram, we derive for Reduced State schemes, new transfer function bounds with the effects of error propagation. Both the Chernoff and the tight upper bound are applied to the transfer function in order to obtain the bit error probability upper bound. Furthermore, and in order to get a tighter bound for Reduced State decoding schemes with parallel transitions, the pairwise probability of the two sequences involved in an error event is upper bounded, and then the branch metric of a sequence taken from that bound is associated with a truncated instead of complete Gaussian noise probability density function. To support the analysis, particular assessment is done for a Trellis Coded Modulation scheme.

This paper proposes a second order auto-regressive equation with discrete-valued random coefficients. The auto-regressive equation transforms an independent stochastic sequence into a binary sequence, which is a special case of a stationary Markov chain. The power spectrum, correlation function and the transition probability are explicitly obtained in terms of the random coefficients. Some computer results are illustrated in figures.

In the applications of the fast Fourier transform (FFT) to real-world computation such as robot vision, high-speed processing with small latency is an important issue. In this paper, we propose a linear array processor for the minimum-latency FFT computation. The processor is constructed by identical butterfly elements (BE's). The key concept to minimize the latency is that each BE generates its output data immediately after its input data become available, with 100% utilization of its arithmetic unit. We also introduce the real-valued FFT to perform the complex-valued FFT. We utilize a double linear array structure so that the parallel processing can be realized without communication between the linear arrays. As a result, the hardware amount of a single BE is reduced to half that of conventional designs. The latency of the proposed FFT processor is greatly reduced in comparison with conventional linear array FFT processors.